• STA Engineer

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
    Broadcom (10/09/25)
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  • SOC Design - STA , Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …that is powering the latest generation of Echo devices is looking for a Senior SoC Design- STA Engineer to continue to innovate on behalf of our customers. We are ... development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. *… more
    Amazon (08/01/25)
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  • STA Principal Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
    Cadence Design Systems, Inc. (08/14/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role...and other I/P DFT integration + Working closely with STA and DI Engineers design closure for test +… more
    Broadcom (09/05/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in...(DV) 3. Support back end physical design (PD) through STA and SDCs 4. Develop system tests in C… more
    Meta (09/09/25)
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  • Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... design, physical design flows, and methodologies including synthesis, place and route, STA , formal verification. - Proven track record of delivering metric driven… more
    Amazon (09/02/25)
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  • Sr. Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... physical design, and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level...in PD tools such as Innovus, ICC2, Fusion Compiler, STA , and Sign-Off. - Proven track record of delivering… more
    Amazon (07/26/25)
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  • Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... with the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
    SpaceX (10/07/25)
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  • ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block timing and… more
    Meta (09/20/25)
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  • Sr. ASIC Design Engineer , Blink/Ring ASIC…

    Amazon (Sunnyvale, CA)
    …of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA -Take the lead and work with verification teams to define functional coverage ... -Work with pre-silicon verification teams to assist in defining testplans/testbenches -Work with post-silicon validation teams to define and execute on testplans -Write high quality documents to guide and lead a scalable team Basic Qualifications -Bachelor's… more
    Amazon (10/18/25)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …it from concept to first customer shipments. **Your Impact** As a Design/CDC Engineer , you will specialize in clock domain crossing (CDC) analysis and closure, while ... development. + Experience with Spyglass CDC and glitch analysis. + Experience with STA tools such as PrimeTime/Tempus. + Experience with scripting languages such as… more
    Cisco (10/17/25)
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