• STA Engineer

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
    Broadcom (10/09/25)
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  • STA Principal Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
    Cadence Design Systems, Inc. (11/13/25)
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  • Physical Design Engineer - Synthesis, PNR,…

    SanDisk (Milpitas, CA)
    …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced...and analysis timing, routing issue in routeOpt stage, + ** STA timing analysis** + MMMC timing analysis using PT… more
    SanDisk (10/10/25)
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  • Physical Design Engineer

    MetaOption, LLC (Milpitas, CA)
    Physical Design Engineer - Milpitas, CA We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and ... experience. Local candidates are preferred. Key Responsibilities: + Pre-layout STA for feasibility and timing constraint validation + Chip/block-level floorplanning… more
    MetaOption, LLC (11/20/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role...and other I/P DFT integration + Working closely with STA and DI Engineers design closure for test +… more
    Broadcom (09/05/25)
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  • Design Implementation Engineer

    Broadcom (San Jose, CA)
    …desired PPA metrics. Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able to implement timing and ... **Requirements:** + Primary expertise in place and route and/ or timing (constraints, STA ) can be considered for this position. + Extremely proficient in design… more
    Broadcom (11/20/25)
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  • HBM/DDR/SerDes DFT Verification Lead…

    Broadcom (San Jose, CA)
    …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
    Broadcom (11/01/25)
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  • Sr Principal Product Engineer - Memory IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …an impact in our world. We are seeking a Post Silicon Memory Product Engineer to support silicon bring-up, debug, and production ramp for advanced memory IP ... presentation, and communication skills. Preferred / Optional Skills + Exposure to STA and RTL flows would be beneficial. + Familiarity with advanced mixed-signal… more
    Cadence Design Systems, Inc. (11/22/25)
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  • Physical Design Engineer

    Broadcom (San Jose, CA)
    …standard cells placements/clock tree adjustments/routing to achieve design specs ( STA /IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required. - ... MSEE/MSCS 6+ years (BSEE/BSCS 8+ years) - Expertise in Cadence Innovus/Atop physical design tools - Experience on Calibre LVS/DRC - Low power, signal integrity experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required,… more
    Broadcom (11/19/25)
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  • Senior Custom ASIC Engineering Lead

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such ... as physical design, STA , DFT, and packaging? Have you taped out so...Our ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in… more
    Broadcom (11/06/25)
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  • ASIC Design Technical Leader - Design & Timing…

    Cisco (San Jose, CA)
    …to first customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
    Cisco (11/18/25)
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