• Senior Full Custom Silicon Engineering…

    Google (Fremont, CA)
    …a highly skilled and experienced Senior Full Custom Silicon Engineering Manager with Customer Owned Tooling (COT) and complementary metal-oxide semiconductor (CMOS) ... Electro Migration (EM), Dynamic/Static Voltage Drop (IR) and Design For Test ( DFT ). + Manage and mentor high-performing Physical Design (PD), Design and Verification… more
    Google (05/16/25)
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  • Manager , Digital Design - Mixed-Signal…

    NVIDIA (Santa Clara, CA)
    Are you looking for a Digital Design Manager role? As a Senior Digital Design Manager in our Mixed-Signal High-Speed I/O SerDes group, you'll lead a team working ... and random testing methodologies + Lead front-end design flows (Lint/CDC/Synthesis/ DFT /LEC/STA) and coordinate with back-end teams for successful chip tape-outs… more
    NVIDIA (03/12/25)
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  • Senior Technical Program Manager , Silicon…

    Google (Sunnyvale, CA)
    …whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary ... that develops hardware and software in data centers. As a Technical Program Manager for Silicon Engineering, you will apply your management abilities and in-depth… more
    Google (05/23/25)
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  • Sr. Technical Program Manager , Advanced…

    Amazon (Sunnyvale, CA)
    Description As a Senior Technical Program Manager , in Amazon's Advanced Products Operations group, you will engage with an experienced cross-disciplinary staff to ... and quality to Amazon's customers. Key job responsibilities As a Technical Program Manager , you will be responsible for bringing new products from engineering to… more
    Amazon (04/26/25)
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  • Technical Program Manager III,…

    Google (Sunnyvale, CA)
    …whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary ... value and quality through test coverage, closed-loop feedback and Design For Testability ( DFT ). Behind everything our users see online is the architecture built by… more
    Google (05/16/25)
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  • Senior Physical Design CAD Manager

    Google (Mountain View, CA)
    …with advanced nodes (eg, 3nm, 2nm). + Familiarity with design for testability ( DFT ) methodologies. + Knowledge of low-power design techniques. Be part of a team ... We are seeking a highly experienced and motivated Senior Physical Design CAD Manager to lead our physical design team and drive the development of advanced… more
    Google (04/22/25)
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  • CPU Cache Subsystem Design Manager

    Google (Mountain View, CA)
    …design team, collaborate with members of architecture, software, verification, power, DFT , physical design teams to define the microarchitecture and schedule in ... delivering high quality RTL that meets project goals. You will help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options… more
    Google (05/29/25)
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  • CPU Arithmetic Dataflow Design Manager

    Google (Mountain View, CA)
    …design team, collaborate with members of architecture, software, verification, power, DFT , physical design teams to define the microarchitecture and schedule in ... delivering high-quality RTL that meets project goals. You will help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options… more
    Google (05/15/25)
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  • ASIC Engineering Technical Leader - SDC

    Cisco (San Jose, CA)
    …Responsibilities include: * Oversee fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing modes. * Assist with ... * Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence). * Experience… more
    Cisco (05/10/25)
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  • ASIC Design Technical Leader - Design & Timing…

    Cisco (San Jose, CA)
    …member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. * Option to also do ... * Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) * Experience… more
    Cisco (05/02/25)
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  • ASIC Design Engineer - Design & Timing Constraints

    Cisco (San Jose, CA)
    …member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. * Option to also do ... * Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) * Experience… more
    Cisco (04/19/25)
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