• High Speed Interfaces

    Qualcomm (Santa Clara, CA)
    …a smarter, connected future for all. Qualcomm is looking for an experienced High Speed Interfaces SOC Architect to work on the next generation AI ... products in the datacenter. We are looking for a High Speed Interfaces data center...for AI Scale Up and Scale Out deployments + Architect enhancements required for deployment of next-generation AI products… more
    Qualcomm (05/19/25)
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  • Signal Integrity Architect

    Qualcomm (Santa Clara, CA)
    …Integrity Architect ** We are seeking an experienced Signal Integrity Architect (individual contributor) to develop high -performance signal integrity (SI) ... suppliers. You will lead the definition, analysis, and verification of SI for high - speed interconnects across die, interposer, package, PCB, and system levels… more
    Qualcomm (03/13/25)
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  • Head of Packaging Development Engineering, Silicon

    Google (Mountain View, CA)
    …to ensure the wider product level Power Delivery Network (PDN) is optimized, all the high speed interfaces (eg, PCIe, USB, UFS, CSI, DSI, LPDDR, etc.) ... the product Power Delivery Network (PDNs). You will also work with the internal/external high speed interface IP teams, implementation teams, and system teams to… more
    Google (05/27/25)
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  • VP of Technology, Virtual Expert Platform (VEP)

    Intuit (Mountain View, CA)
    …prospects and customers. We own the entire technology stack, from user interfaces and expert management systems to workforce operations, digital expertise and ... in platform development, architecture, and scaling + Experience in leading high -performing engineering teams + Deep understanding of cloud computing, microservices,… more
    Intuit (05/21/25)
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  • Senior Principal Engineer (Cortex Xpanse)

    Palo Alto Networks (Santa Clara, CA)
    …mitigate risks in ongoing and planned projects to ensure smooth execution and high output - This may include providing ad hoc mentorship, communicating with project ... Design, build, and optimize data models and queries for speed and scale, using data storage technologies like MySQL...API endpoints using Python and Flask + Build user interfaces using Angular **Your Experience** + 8+ years of… more
    Palo Alto Networks (05/22/25)
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  • Design Engineering Director

    Cadence Design Systems, Inc. (San Jose, CA)
    …team of engineers * Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/ PCIe/CXL/UCIe/ * Debug skills and Experience in ... develop calibration / compliance lab suites and characterize. + Architect and design Printed circuit boards in Schematic and...in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and… more
    Cadence Design Systems, Inc. (04/09/25)
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  • ASIC FPGA Design and Verification Engineer…

    The Boeing Company (Mountain View, CA)
    …developing Functional Coverage Models and Closing Code Coverage + Experience with high - speed Serdes interfaces (JESD204C, PCIe, Ethernet) + Proficient ... provide some of the most complex SoCs in the world. We develop robust, high -performance custom processors using the latest ARM IP to enable high -integrity, low… more
    The Boeing Company (05/24/25)
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