- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role you will be working on ... with timing ECO creation and final timing signoff. + Proficiency in using STA tools (eg, PrimeTime, Tempus) and scripting languages (eg, Tcl, Perl). + Proficiency… more
- Qualcomm (Santa Clara, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for RTL-Synthesis and ... PrimeTime- STA for the blocks and the top-level including SOC....Hierarchical Constraints for Functional & DFT Modes. 4. Perform STA for full chip and Physical partition blocks using… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze the… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking… more
- Microsoft Corporation (Santa Clara, CA)
- …DPU's compute, storage, and networking capabilities. We are seeking a **Senior Physical Design Engineer ** . As part of our DPU silicon team in Santa Clara, you will ... of flows and automation for key physical design tools (place & route, extraction/ STA , physical verification, etc); deploy and test new flows; debug issues & improve… more
- Qualcomm (Santa Clara, CA)
- …proactively find solutions. This candidate will be working with Design, Synthesis and STA teams closely to provide physical design feedback and improve the overall ... in Floor Planning (FP), Placement, Clock Tree Synthesis (CTS), STA closure, and Physical verification closure for critical WiFi...is a must. - Debugging capability for PV and STA flows is preferred. - UPF knowledge is preferred.… more
- Cisco (San Jose, CA)
- …of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a ... the boundaries of what's possible! Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints,… more
- NVIDIA (Santa Clara, CA)
- …We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... SNPS TCM ) and debug anomalies in timing reports. + Support tapeout-quality STA environments that are scalable, reusable, and validated through both structural and… more
- Meta (Sunnyvale, CA)
- …for large complex disaggregated ASICs, with exposure to library characterization, STA , modeling, extraction, variation analysis, aging, and signoff flows to build ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ASIC vendor partners and Foundries… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... design, physical design flows, and methodologies including synthesis, place and route, STA , formal verification. - Proven track record of delivering metric driven… more
- SpaceX (Sunnyvale, CA)
- SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- NVIDIA (Santa Clara, CA)
- …intelligence. We are seeking an innovative senior timing and VF Methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... experience in ASIC Design and Timing. + Knowledge of device physics, STA methodology. + Good understanding of mathematics/physics fundamentals of electrical design.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... tools + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs +… more
- Qualcomm (Santa Clara, CA)
- …push the envelope on performance, energy efficiency and scalability. As CPU EM/IR CAD engineer , you will build and support the world's best analysis tools and flows. ... user of Ansys Redhawk SC power integrity analysis toll and have exposure to PnR/ STA and extraction industry standard tools and flow + Support and enhance static IR,… more
- NVIDIA (Santa Clara, CA)
- …tools + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + ... world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! #LI-Hybrid… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** R&D Engineer position available in design and physical implementation of high performance ... design tools for Place&Route, Verilog simulation, DRC/LVS verification, Timing analysis ( STA ), Scripting languages - Tcl?Perl/ Python + Proficiency in UNIX/Linux… more
- Meta (Sunnyvale, CA)
- …to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block timing and… more