• Sr . IC Layout

    SpaceX (Sunnyvale, CA)
    Sr . IC Layout Engineer (Starlink) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... the ultimate goal of enabling human life on Mars. SR . IC LAYOUT ENGINEER...meet critical milestones COMPENSATION AND BENEFITS: Pay range: Silicon Engineer / Senior : $140,000.00 - $190,000.00/per year Your actual… more
    SpaceX (04/15/25)
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  • Senior Analog, Custom IC Design/…

    Cadence Design Systems, Inc. (San Jose, CA)
    …and verbal communication skills. Responsibilities include: + Understanding customers' custom IC design, simulation and layout challenges + Guiding customer ... + Minimum 3 years of practical hands-on experience in simulation and/or layout applications for Custom IC Design. Analog, mixed-signal or RF design or layout more
    Cadence Design Systems, Inc. (04/12/25)
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  • Sr . Staff IC CAD Engineer

    Power Integrations (San Jose, CA)
    …software installation, license management, user support and vendor interface. + Works with IC layout designers providing support for taping out physical designs ... and power density. We are seeking a highly motivated Sr . Staff CAD Engineer to join our...Responsibilities + Develops and maintains PDKs. + Supports all IC design CAD tools such as Cadence schematic entry,… more
    Power Integrations (04/16/25)
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  • Photonic IC Design Engineer

    Applied Materials (Santa Clara, CA)
    …integrated products of the connectivity solutions for Applied Materials. It is a senior engineer that initiates initial blueprints of the products & solutions ... to learn more about careers at Applied. The Photonic IC Design Engineer is responsible for the...optical) for high speed architectures. + Create schematics and layout circuits. + Work with test and firmware engineering… more
    Applied Materials (05/10/25)
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  • Senior Analog Layout Engineer

    Capgemini (Santa Clara, CA)
    **About the job you're considering** We are seeking a Senior Analog Layout Design Engineer with deep expertise in advanced CMOS FinFET technologies (TSMC ... **Your skills and experience** + Proficient in developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies… more
    Capgemini (05/28/25)
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  • Senior Analog Layout Engineer

    Capgemini (San Jose, CA)
    **Job description:** ** Senior Analog Layout Engineer ** will be responsible for layout of high-performance analog cores such as analog-to-digital ... converters, digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS… more
    Capgemini (04/18/25)
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  • RF/Analog IC Design Engineer

    Qualcomm (Santa Clara, CA)
    …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director and above). **Principal Duties and Responsibilities:** * Leads ... perform under various circumstances. * Lead others to floor-plan layout ; collaborates with layout engineers to generate...influence over key organizational decisions (eg, is consulted by senior leadership to provide input on key decisions). *… more
    Qualcomm (05/29/25)
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  • RF/Analog IC Design Engineer

    Qualcomm (Santa Clara, CA)
    …organization. * 2+ years of work experience in a role requiring interaction with senior leadership (eg, Director and above). * 2+ years in a technical leadership ... perform under various circumstances. * Leads team to floor-plan layout ; collaborate with layout engineers to generate...influence over key organizational decisions (eg, is consulted by senior leadership to provide input on key decisions). *… more
    Qualcomm (05/29/25)
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  • Senior Package Layout

    NVIDIA (Santa Clara, CA)
    …in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in ... different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams… more
    NVIDIA (05/21/25)
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  • Senior Failure Analysis Engineer

    Power Integrations (San Jose, CA)
    …communication will be given special consideration. + Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar ... Job Description: The Senior Failure Analysis Engineer will perform...Perform fault isolation and defect analysis/ characterization on power IC 's to identify root causes of product failures in… more
    Power Integrations (04/08/25)
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  • Senior Staff Analog Engineer

    Renesas (San Jose, CA)
    Senior Staff Analog Engineer Job Description +...system and design strategy for custom ASICs. + Guide layout team to ensure quality of layout of ... have a consulting function in design reviews + Reviews IC design, evaluation, characterization and test results. + Schedule...high performance analog IP's, DC-DC, and FPGA. As a Senior Analog Staff Engineer , you will design… more
    Renesas (05/24/25)
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  • Senior Electrical Engineer

    Applied Materials (Santa Clara, CA)
    …using glass, organic, or silicon substrates/interposers, ensuring high performance and reliability.. IC Packaging and PCB Layout : Support the design of ... performance, reliability, and manufacturability.. Simulation Tools: Utilize industry-standard PCB layout and simulation tools to streamline design workflows and… more
    Applied Materials (05/28/25)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    …come join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation ... Help by defining circuit requirements and complete design from schematic, layout , and verification to characterization. + Conduct schematic design of deep-submicron… more
    NVIDIA (05/27/25)
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  • Mixed Signal Design Engineer - New College…

    NVIDIA (Santa Clara, CA)
    …come join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation ... PLLs. + Define circuit requirements and complete design from schematic, layout , and verification to characterization. + Conduct schematic design of deep-submicron… more
    NVIDIA (05/08/25)
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  • Power Delivery Network Engineer

    Qualcomm (Santa Clara, CA)
    …+ 4+ years of work experience in a role requiring interaction with senior leadership (eg, Director level and above). **Principal Duties and Responsibilities:** + ... route, timing and power use, and verification or similarly for custom circuit design/ layout flow. + Utilizes tools/applications (eg, RTL to GDS Flow, Virtuoso) to… more
    Qualcomm (05/14/25)
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