- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level RTL synthesis engineer . In this highly visible role, you will ... years of experience in Physical design.** + **Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist… more
- Broadcom (San Jose, CA)
- …apply.** **Job Description:** **Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include:** + **MS or PhD in Electrical Engineering or ... years of experience in high speed ADC based SerDes RTL design.** + **Proficient with Verilog-HDL/System Verilog coding for...and cost over the project lifetime.** + **Experience in synthesis , CDC, static timing analysis.** + **Exposure to SDF… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design, debug and functional verification + Strong background in DSP and ... of Lint checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding… more
- Microsoft Corporation (Mountain View, CA)
- …augmented reality. We are looking for a ** ** **Principal** **Design** **Technical Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip ... You will be responsible for developing and maintaining the RTL design flows and methodologies for our cutting edge...tools, flows and methodologies such as Lint, CDC, RDC, Synthesis + 8+ years of experience in architecting and… more
- Google (Mountain View, CA)
- …IP design. + Experience with methodologies for low power estimation, timing closure, synthesis . + Experience with methodologies for RTL quality checks (eg, Lint, ... ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain...RTL development (SystemVerilog), debug functional/performance simulations. + Perform RTL quality checks including Lint, CDC, Synthesis ,… more
- ManpowerGroup (Mountain View, CA)
- Our client, a leader in the technology sector, is seeking a Hardware Design Engineer 5 to join their team. As a Hardware Design Engineer 5, you will be part of ... align successfully in the organization. **Job Title:** Hardware Design Engineer 5 **Location:** Austin, TX and Mountain View, CA...**Pay Range:** **What's the Job?** + Design and implement RTL for image and video processing IP blocks. +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …R&D teams to win opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP demos to customers* ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob...presales of DDR IP by generating collateral through simulations, synthesis and publications. As you grow into more senior… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on the world of technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The Cadence DSG ... You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies...with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong history of self-improvement… more
- Google (Mountain View, CA)
- …design concepts, and languages such as Verilog or SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well ... TPU Design Engineer , Silicon _corporate_fare_ Google _place_ Mountain View, CA,...ensure functionality of the design. + Provide input on synthesis , timing closure, and Physical Design of digital blocks.… more
- Microsoft Corporation (Mountain View, CA)
- …working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level ( RTL ) design, synthesis /Lint/CDC/FEV and System on Chip (SOC) ... to help achieve that mission. We are looking for a **Senior** **Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC)… more
- Google (Fremont, CA)
- Staff Silicon Design Engineer , Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, solving ambiguous ... 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or...languages such as Verilog or SystemVerilog. + Experience of synthesis and static timing analysis. + Experience in silicon… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to highly integrated ... languages such as Tcl or Perl. + Provide guidance on clock tree synthesis and optimization for energy-efficient designs. + Ensure compliance with timing signoff… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …simulation and synthesis tools . Strong knowledge of ASIC flow, RTL /Verilog . Individual leadership and initiative to manage pre-sales accounts . Excellent ... Join the High-Performance Culture at Cadence. As a Lead Technical Presales Engineer , you will use your knowledge of different memory interface standards to… more
- quadric.io, Inc (Burlingame, CA)
- …processor architecture by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog + Own ... computing + Experience in FPGA design is a plus + Experience in logic synthesis and performance modeling Nice to haves: + Familiarity with automotive safety (ASIL)… more
- Cisco (San Jose, CA)
- …it from concept to first customer shipments. **Your Impact** As a Design/CDC Engineer , you will specialize in clock domain crossing (CDC) analysis and closure, while ... also contributing to RTL design and microarchitecture development. You will ensure robust...concepts (eg. clocking and async boundaries). + Experience with synthesis tools (eg. Synopsys DC/DCG/FC) and Verilog/System Verilog programming.… more