- NVIDIA (Santa Clara, CA)
- …us today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order ... has increased significantly. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints. What… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... memory BIST, scan and array dump and DFX security methodology . + In addition, you will help develop and...Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we… more
- NVIDIA (Santa Clara, CA)
- …to join us today. We are now looking for a highly motivated DFT Engineer to join this dynamic and innovative hardware team at NVIDIA. Our Design-for-Test Engineering ... for the most complex chips in the world, from methodology , to deployment to post-silicon lifecycle support. + Partner...+ Good exposure to multiple domains including RTL & clocks design, STA, place-n-route and power, to ensure we… more