- Meta (Columbus, OH)
- …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Sunnyvale, CA)
- …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Austin, TX)
- …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP /SoC verification plans, ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Austin, TX)
- …first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/ IP /SoC verification ... **Summary:** Meta is hiring ASIC Design Verification Engineer ...organization. We are looking for individuals with experience in Design Verification to build IP and System… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer , you will be ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Develop… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...CDC, Synthesis, & Power Optimization 5. Soft and hard IP identification, selection and integration 6. Collaboration with verification… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...CDC, Synthesis, & Power Optimization. 4. Soft and hard IP identification, selection and integration. 5. Collaboration with verification… more
- Meta (Menlo Park, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Verilog, System Verilog and HLS. 4. Soft and hard IP identification, selection and integration. Collaboration with verification and… more
- Meta (Austin, TX)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...Verilog, System Verilog and HLS 4. Soft and hard IP identification, selection and integration 5. Collaboration with verification… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... 3. Deliver physical design of an end-to-end IP or integration of ASIC /SoC design...to $203,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an… more
- Amazon (Cupertino, CA)
- … design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze...innovate, explore new solutions, and contribute to the company's intellectual property through patents About the team… more
- NVIDIA (Austin, TX)
- …can make a lasting impact on the world. Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on ... improving methodologies and delivering system-level IP to measure performance across multiple projects. What you'll...system + Run and debug RTL checks to ensure design quality (eg, cross clock domains (CDC), clocks, reset,… more
- Meta (Austin, TX)
- …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC , Design Verification Engineer Responsibilities: 1. Develop functional tests ... based on verification test plan. 2. Drive Design Verification to closure based on defined verification metrics...verification 8. 2. Track record of 'first-pass success' in ASIC development cycles 9. 3. Block/ IP /sub-system and/or… more
- Northrop Grumman (Baltimore, MD)
- …for you to join our team as a Principal Digital Engineer /Senior Principal Digital Engineer (FPGA and ASIC Design ) based out of Linthicum, MD. **What ... Program Access (SAP) + Experience with industry standard FPGA design implementation tools for IP integration, PnR,...(requirements, design , implementation and test) of FPGA Design and/or ASIC Design +… more
- Cisco (San Jose, CA)
- …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... of what's possible! Your Impact You are a diligent Design /SDC Engineer with strong analytical skills and...modes. * Option to also do block level RTL design or block or top-level IP integration.… more
- Google (Mountain View, CA)
- …with an emphasis on computer architecture. + 8 years of industry experience with IP design . + Experience with methodologies for low power estimation, timing ... or equivalent practical experience. + 5 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with a scripting… more
- Google (Mountain View, CA)
- …Science, with an emphasis on computer architecture. + 3 years of experience with Intellectual Property ( IP ) design for clocking, interconnects or ... experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages... techniques. + Experience with ARM-based SoCs, interconnects and ASIC methodology. + Experience with a scripting language like… more
- Qualcomm (San Diego, CA)
- …Engineering Group > ASICS Engineering **General Summary:** Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join ... definition of the high-speed interfaces - Define, document and design the microarchitecture of IP blocks -...- Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT,… more
- Google (Sunnyvale, CA)
- …AI acceleration. In this role, you will design Register-Transfer Level (RTL) Intellectual Property ( IP ) with a focus on chip-to-chip interconnect ... of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design Engineer , you will play an important role in designing… more
- Qualcomm (San Diego, CA)
- …applications. QCT mixed-signal design team consists of architects and ASIC designers, protocol experts, signal processing engineers, and algorithm designers ... Mixed Signal Design **General Summary:** QCT mixed-signal IP design team is looking for talented...course selections and/or work experience. + Experience working with ASIC design tools such as Cadence Virtuoso.… more