• Advanced Micro Devices, Inc (San Jose, CA)
    …AMD together we advance_ THE ROLE: AMD is seeking a ASIC Design Engineer with specific experience with scripting skills around the EDA tool environments to ... flow which performs implementation of RTL through pre-netlist synthesis and static timing analysis. He/She will also develop parsers to extract and waive key… more
    Upward (07/01/25)
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  • Principal Timing /STA Engineer

    Microsoft Corporation (Hillsboro, OR)
    …optimize the Cloud infrastructure. We are looking for a **Principal Timing /STA Engineer ** to join the team. **Responsibilities** + Lead the STA ... methodology development and execution to meet timing closure targets for complex semiconductor designs. + Collaborate...implementation, and physical design teams to define and drive timing constraints and methodology . + Conduct … more
    Microsoft Corporation (07/22/25)
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  • Senior Post-Silicon Validation…

    NVIDIA (Santa Clara, CA)
    …complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is ... + Build supporting tools/script/infrastructure with relevant stakeholder teams. + Lead post-silicon bringup and support debug activities. + Continuously optimize… more
    NVIDIA (06/13/25)
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  • Staff Lead Design Verification…

    Northrop Grumman (Annapolis Junction, MD)
    …to make these technologies a reality. **What You'll Get To Do:** As a Digital Verification Lead Engineer , you will have an opportunity to be a part of a ... Integration & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our...and resolve signal delay and performance issues in gate timing requirements + Develop comprehensive Universal Verification Methodology more
    Northrop Grumman (07/18/25)
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  • Staff Lead Design Verification…

    Northrop Grumman (Annapolis Junction, MD)
    …to make these technologies a reality. **What You'll Get To Do:** As a Digital Verification Lead Engineer , you will have an opportunity to be a part of a ... The Systems Engineering Integration & Test (SEIT) department is seeking a **Staff Lead Design Verification Engineer ** to join our team and develop these… more
    Northrop Grumman (07/18/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …who want to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: ... Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).You may get involved in design services projects and/or… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Lead Speed and Reliability Engineer

    NVIDIA (Santa Clara, CA)
    …Productization, DFP for short, is a group within SSG with focus on SOL methodology , design, testplan and tools to efficiently enable, test and deploy new chip ... DFP team is looking for a Speed and Reliability Lead . You will be leading and crafting testability features...be leading and crafting testability features related to Speed, Timing and Reliability from ground up as you help… more
    NVIDIA (05/29/25)
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  • Computer Architect/Embedded Computing Systems…

    The Boeing Company (El Segundo, CA)
    …Weapons Systems has an exciting opportunity for a **Computer Architect/Embedded Computing Systems Design Engineer ( Lead or Senior)** to join us as part of our ... aerospace applications, we have an exciting opportunity for you. As a Computer Engineer Architect on our SI&WS Electronics team at Boeing Space, Intelligence &… more
    The Boeing Company (07/10/25)
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  • I/O Modeling and Characterization Engineer

    Qualcomm (San Diego, CA)
    …Group > ASICS Engineering **General Summary:** This is aI/O modeling and characterization lead position in Methodology , Flow and Design Kit team involved in ... defining methodologies, flows and in delivering design kit including behavioral models and timing models for I/Os, memories and standard cell libraries in state of… more
    Qualcomm (06/27/25)
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  • Design Release Engineer

    General Motors (Warren, MI)
    …Change Management Processes; Component Design Review; Technical Design Review; Waterfall methodology ; Pugh Matrix; Program timing and milestones; Kano Diagrams; ... inverter design and parts lists development. Developing and executing project timing plans. Initiating and executing engineering change requests, material orders,… more
    General Motors (06/29/25)
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  • Senior Reliability Engineer

    GE HealthCare (Waukesha, WI)
    **Job Description Summary** The Senior Reliability engineer will be an integral part of the central DFR (Design for Reliability) program team within the STO org ... support the development and deployment of the standard GEHC DFR methodology applying relevant reliability concepts, processes, standards, and tools. Activities… more
    GE HealthCare (05/22/25)
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  • EMC Vehicle Test Engineer

    General Motors (Milford, MI)
    …times per week, at minimum. **The Role:** For our role of EMC Vehicle Test Engineer , you will have the opportunity to exhibit expertise and training of a senior ... engineer . This role manages most project responsibilities, rather than...efficient plan with reduced number of redundant tests. Balance timing and number of tests for right mix of… more
    General Motors (07/15/25)
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  • Senior Staff Data Engineer - Hybrid

    The Hartford (Chicago, IL)
    …and Performed Dynamic data Masking. + Have a solid understanding of delivery methodology (SDLC) and lead teams in the implementation of the solution according ... Sr Staff Data Engineer - GE07DE We're determined to make a...Performance Tuning of Jobs to reduce the CPU time/load timing . + Deeper Knowledge on SnowFlake License model and… more
    The Hartford (07/02/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …functional verification **Preferred Qualification:** + DFT CAD development - Test Architecture, Methodology and Infrastructure + Test Static Timing Analysis + ... Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US...Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus… more
    Cisco (07/22/25)
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  • Environmental Engineer 5

    CDM Smith (Boston, MA)
    …**Business Unit:** TSU **Job Description:** CDM Smith is currently seeking an Environmental Engineer in the Boston, MA office to support a wide variety of ... external client interaction and marketing skills. **Job Title:** Environmental Engineer 5 **Group:** ESO **Employment Type:** Regular **Minimum Qualifications:**… more
    CDM Smith (07/18/25)
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  • ASIC Implementation Engineer

    Broadcom (San Jose, CA)
    …including synthesis, design for test, floorplanning, place and route, clock methodology , power planning and analysis, timing closure, signal integrity ... large complex design implementations using the latest technology nodes, lead one or more disciplines in design closure as...results. + Complete tasks with little supervision, able to lead projects and set direction for other project members.… more
    Broadcom (06/03/25)
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  • Senior DDR Subsystem Verification Engineer

    Microsoft Corporation (Hillsboro, OR)
    …the Cloud infrastructure. We are looking for a **Senior DDR Subsystem Verification Engineer ** to join the team. **Responsibilities** + Own or lead verification ... + Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and… more
    Microsoft Corporation (07/12/25)
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  • Senior Engineer - Process Development

    DuPont (Circleville, OH)
    …**DuPont** has an exciting and challenging opportunity for a **Process Development Engineer ** in the **Vespel(R), R&D group** within the Electronics & Industrial ... trends and innovations in polymer manufacturing and processing technologies. + Lead projects aimed at raw material qualification and risk mitigation, ensuring… more
    DuPont (07/04/25)
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  • CPU Physical Design - Low Power Signoff…

    Qualcomm (San Diego, CA)
    …to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that ... Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + Should have good exposure to high… more
    Qualcomm (06/05/25)
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  • Senior Staff Software Engineer

    Stryker (Flower Mound, TX)
    As a Senior Staff Software Engineer at Stryker, you will independently design and implement complex systems including application software architecture and the ... system requirements. You will apply the defined design practices including Agile methodology and use sound software engineering principles to ensure that the… more
    Stryker (05/29/25)
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