- Qualcomm (Austin, TX)
- …Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > DSP Architecture and Design **General Summary:** You will be part of an exciting design ... an extraordinary opportunity in a highly visible role for Power UPF Engineers to perform power intent/UPF... definition. **Qualifications** + Experience or familiarity with ASIC design flows + Sound knowledge of basic circuit and… more
- SpaceX (Irvine, CA)
- Sr. ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity ... with the ultimate goal of enabling human life on Mars. SR. ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Qualcomm (Austin, TX)
- …Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer , you will work with implementation and ... CAD teams to implement the designs meeting aggressive power , area and performance goals using industry standard tools/flows for next generation CPUs.… more
- Google (Mountain View, CA)
- …software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the ... + 5 years of experience with SoC Integration focused on low power design . + Experience with new process technology based SoC integration flow development… more
- Google (Sunnyvale, CA)
- …software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the ... static timing analysis, CDC, formal verification, physical verification, and power integrity. + Collaborate with chip design ...and power integrity. + Collaborate with chip design teams to implement flows and methodologies to improve… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical ... and below process technologies. Nice to haves: + Knowledge of lower power digital design techniques. + IP integration experience. + Experience in data parallel… more
- NVIDIA (Santa Clara, CA)
- …experience in Physical Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, ... varied strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. + Key responsibility… more
- Micron Technology, Inc. (Atlanta, GA)
- … on RTL, gate, and transistor level. + Deep knowledge of IP and SoC design flows and methodologies (CDC, Synthesis/STA, Power ) + Experience in design ... or equivalent, simulate to verify proper circuit operation. Familiarity with Cadence Design Framework. Analyze circuits for power consumption, speed performance,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... memory BIST, scan and array dump and DFX security methodology . + In addition, you will help develop and...exposure to cross functional areas including RTL & clocks design , STA, place-n-route and power , to ensure… more
- NVIDIA (Santa Clara, CA)
- …today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order to ... design needs to balance high frequency clocks with power , DFT, noise, circuit and physical design constraints. What you'll be doing: + Develop Clock RTL… more
- NVIDIA (Santa Clara, CA)
- …+ Engage with EDA providers on 3D-IC EDA feature requirements and 3D-IC design methodology . + Design optimization of 3D advanced silicon/package ... 3D-IC Test Chips validation of 3D-IC technology platforms and design methodology . What we need to see:...and/or Product designs. + Multiple clock domain and Low Power Design . + Expertise with Python, TCL… more
- Qualcomm (Austin, TX)
- …QUALCOMMs Adreno Graphics cores in the area of Low Power implementation and methodology . The Power Implementation Engineer will work in QUALCOMMs Adreno ... and Optimization, Performance Power and Area modeling and optimization, SOC Design implementation / methodology , Synthesis, Semi-custom design flow and … more
- Qualcomm (Santa Clara, CA)
- …Power verification team, you will be responsible for verifying the ASIC low power design , architecture and micro-architecture of by applying advanced low ... Engineering **General Summary:** We are looking for an ASIC Design Verification Engineer with strong CPU, ASIC...impact in shaping 5G product lines ranging from low power Snapdragon chips to the growing field of Machine… more
- Amazon (Austin, TX)
- …it's still Day One here at Amazon! We're searching for an experienced Frontend ASIC engineer with a background in RTL design and/or verification with a proven ... (MLA) team develops the SOCs that are used to power today's AI workloads in datacenters all around the...datacenters all around the world. As a Frontend ASIC engineer , you'll contribute to the project at the ground… more
- ManpowerGroup (Phoenix, AZ)
- **Role: Physical Design - Power Integrity Flow Development Engineer ** **Location: Phoenix, AZ** **Experience: 9 years** **Job Description** + Perform ... integrity issues related to physical design , identify potential low power solutions, drive execution and methodology improvements. **Basic Qualifications:**… more
- Qualcomm (Santa Clara, CA)
- …and power correlation. + Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power ... in CPU sub system-based design is preferred + Experience in low power design from project start to volume chip production for atleast one product cycle is… more
- Qualcomm (San Diego, CA)
- …development of next Generation, high performance, low power Memory Subsystem RTL Design , flows and methodology for high performance ASICs in sub-4nm process ... power , high performance ASIC designs, and, ability to execute critical power analysis of critical design IPs for path to DDR. This is a great opportunity to… more
- BAE Systems (Westminster, CO)
- …incentives may be available based on position level and/or job specifics. **Analog and Power Design Engineer II** **101755BR** EEO Career Site Equal ... performance requirements. + Define and implement test and verification methodology at the board level and provide support at...related software. + Well versed in circuit-level switch mode power supply design and analog electronics using… more
- Micron Technology, Inc. (Atlanta, GA)
- …that are transforming how the world uses information to enrich life. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing ... technology development and advanced memory designs to product development, systems design , and validation resulting in world-class memory solutions. Our team vision… more
- Qualcomm (Austin, TX)
- …with various bus protocols like AHB, AXI, SPMI, I2C, SPI + Experience in low power design methodology and clock domain crossing designs + Experience in ... create a smarter, connected future for all. Candidate will be responsible for design /developing next generation power control systems. Candidate will be working… more