- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level RTL synthesis engineer . In this highly visible role, you will ... years of experience in Physical design.** + **Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist… more
- Silvus Technologies (Irvine, CA)
- …fundamentals using Verilog and System-Verilog. + Proven expertise working with front-end RTL design tools, FPGA synthesis , timing closure, multiple clock-domain ... fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Principal FPGA / RTL Design Engineer_** who will report to the _Senior Engineering Director for… more
- Silvus Technologies (Irvine, CA)
- …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for ... projects aimed at addressing challenging real-world communication needs. The Principal FPGA / RTL Design Engineer position will be based at Silvus' Irvine CA… more
- Amazon (Boise, ID)
- …tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As an RTL Design Engineer , you will be part of an advanced architecture team that is ... - Develop detailed design specifications and documentation - Perform RTL coding and synthesis - Work with Partners/Supplier to optimize and customize their… more
- Silvus Technologies (Irvine, CA)
- …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA / RTL Design Engineer_** reporting to the _Director of FPGA Engineering_ on the FPGA ... projects targeted to address challenging real-world communication needs. The _Senior FPGA / RTL Design Engineer_ position will be based at Silvus headquarters in the… more
- Broadcom (San Jose, CA)
- …apply.** **Job Description:** **Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include:** + **MS or PhD in Electrical Engineering or ... years of experience in high speed ADC based SerDes RTL design.** + **Proficient with Verilog-HDL/System Verilog coding for...and cost over the project lifetime.** + **Experience in synthesis , CDC, static timing analysis.** + **Exposure to SDF… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design, debug and functional verification + Strong background in DSP and ... of Lint checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding… more
- Cadence Design Systems, Inc. (Austin, TX)
- …projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in ... be responsible for: Technical Leadership: Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design &… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and gate ... CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and...synthesis and integration. + Deep understanding of Verilog RTL design and digital design principles. + Proven experience… more
- SanDisk (Milpitas, CA)
- …**Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include Synthesis , DFT scan insertion, PNR, STA timing analysis, ... ICC2, Innovus, PT, StarRC ESSENTIAL DUTIES AND RESPONSIBILITIES: + ** Synthesis and DFT scan insertion** + Familiar timing constraint...A minimum of 3 years in Physical design digital RTL to GDS flow. + **Education** : Bachelor's or… more
- NVIDIA (Santa Clara, CA)
- …methodologies + Build flows for methodologies incorporating logic/physical synthesis , design planning, equivalence checking for industry-leading chip designs ... , Tcl, C/C++ + Knowledge or experience with logic synthesis , physical design, formal equivalence checking. + Proven track...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- SanDisk (Milpitas, CA)
- …all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis , and timing analysis to deliver a ... of innovation. We are looking for an experienced Principal Engineer to lead and deliver projects for our Memory...Logic design flow from RTL to GDSII ( RTL coding, simulation, synthesis , static timing analysis,… more
- SanDisk (Milpitas, CA)
- …all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis , and timing analysis to deliver a ... of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory...Logic design flow from RTL to GDSII ( RTL coding, simulation, synthesis , static timing analysis,… more
- Meta (Sunnyvale, CA)
- …"Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL - synthesis and PrimeTime-STA for blocks and top-level including SOC. 11. Analyze… more
- Microsoft Corporation (Raleigh, NC)
- …years of experience in Digital Design, encompassing microarchitecture specification, RTL coding (Verilog/SystemVerilog), CDC/Lint closure, synthesis , timing ... that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence...+ Own and drive the development of microarchitecture and RTL design, coding, and verification of complex IP blocks,… more
- Renesas (Austin, TX)
- …linting, and CDC/RDC checking + Knowledge of asynchronous clock crossings and synthesis implications of RTL + Experience implementing and verifying ECOs ... Principal Digital Design Engineer Job Description Renesas is seeking a talented...DDR6, and beyond. **Responsibilities:** + Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated… more
- NVIDIA (Austin, TX)
- …on the world. Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering ... integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs +… more
- Insight Global (Colorado Springs, CO)
- …in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out. Responsibilities include: -Execution of Physical Design, ... Synthesis , Physical Verification, and Timing Closure -Setup and Synthesizing RTL -Timing closure through various methods and strategies -EM/IR Analysis -Place and… more
- NVIDIA (Santa Clara, CA)
- …performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis /timing clean design. ... We are now looking for an ASIC Design Engineer ! NVIDIA has been transforming computer graphics, PC...caches. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing… more
- Google (Mountain View, CA)
- …IP design. + Experience with methodologies for low power estimation, timing closure, synthesis . + Experience with methodologies for RTL quality checks (eg, Lint, ... ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain...RTL development (SystemVerilog), debug functional/performance simulations. + Perform RTL quality checks including Lint, CDC, Synthesis ,… more