- Cadence Design Systems, Inc. (Austin, TX)
- …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
- Microsoft Corporation (Redmond, WA)
- …that will manage and optimize the Cloud infrastructure. We are looking for a ** Principal Timing/ STA Engineer ** to join the team. **Responsibilities** + Lead ... the STA methodology development and execution to meet timing closure targets for complex semiconductor designs. + Collaborate with design, implementation, and… more
- Qualcomm (Santa Clara, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... in Tcl, Perl, or Python are also desirable. **Job Description: Principal Duties and Responsibilities** + Develop constraints for physical power-aware synthesis,… more
- Xcel Energy (St. Paul, MN)
- …skills and experience as different skills and/or experience will be required at the entry, sta ** **ff and principal ** ** engineer levels.** We are seeking a ... Engineer ) registration may be required depending on business need. ** Principal Engineer (Salary Range: $109,300-$152,766)** **Minimum Requirements** +… more
- Qualcomm (San Diego, CA)
- …preferred. ** Principal Duties and Responsibilities:** * Participate to the STA and Cell Characterization flows and features enablement for foundry advanced ... developing good-by-construction hierarchical solution, as well as enabling the latest STA features to reduce conservatism in Signoff. **This role's responsibilities… more
- Qualcomm (San Diego, CA)
- …to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that have a ... in IC design** . + **Experience in leading block level or chip level Physical Design, STA and PDN activities** . + Work independently in the areas of RTL to GDSII… more
- Qualcomm (Santa Clara, CA)
- …push the envelope on performance, energy efficiency and scalability. As CPU EM/IR CAD engineer , you will build and support the world's best analysis tools and flows. ... user of Ansys Redhawk SC power integrity analysis toll and have exposure to PnR/ STA and extraction industry standard tools and flow + Support and enhance static IR,… more