- NVIDIA (Austin, TX)
- …and intelligence. The NVIDIA System-On- Chip (SOC) group is looking for a top Senior ASIC Verification Engineer! In this position you will have the chance to ... and SOC). What you'll be doing: + Design and maintain the Full Chip Verification environment. + Understand the architecture specifications and develop the test… more
- Palo Alto Networks (Santa Clara, CA)
- …an environment where we all win with precision. **Your Career** We are looking for a Senior Director of ASIC Engineering to manage and lead a high performing ... in-person interactions. This is why our employees generally work full time from our office with flexibility offered where...teams + Recent experience in networking or network security chip developments + Prior experiences in digital ASIC… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. + Analyze and optimize design constraints and synthesis parameters to… more
- NVIDIA (Santa Clara, CA)
- …and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Work with PD, DFX, Clocks, and other teams in coming ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Timing and STA + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA)… more
- NVIDIA (Santa Clara, CA)
- …of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend implementation including ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Synthesis and Timing + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA),… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... experience. + 8+ years experience in Physical design/Timing. + Experience in full - chip /sub- chip Static Timing Analysis (STA), timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... plans and verification infrastructure and tests. Support functional and DFT full chip level verification efforts + Support post-silicon bring up and validation… more
- Amazon (Austin, TX)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic ... of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.… more
- Amazon (Cupertino, CA)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning… more
- Tarana Wireless (Milpitas, CA)
- …software engineers to define verification strategies and execute plans at system or full chip level + Build and continuously improve verification infrastructure ... and methodologies to meet the demands of next generation SoCs + Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project Ways to stand out from the crowd: + Ability… more
- Amazon (Sunnyvale, CA)
- …low-latency, high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining EDA ... the versions of the tools, flows, design IPs, other collateral for every chip in development. Additionally, you will interface various digital design teams who will… more
- Capgemini (CA)
- …semiconductor companies. **Your Role** + Lead, inspire, and scale a team of senior sales executives and subject matter experts, creating a culture of performance, ... that position Capgemini as a trusted partner across the semiconductor lifecycle-from chip design and embedded software to hardware, supply chain, and sustainability.… more
- Qualcomm (Santa Clara, CA)
- …The candidate will work hands-on and own their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, ... correlation. The candidate will also be responsible for the full chip debug design using ARM IPs....will work hands-on and own their design through the full ASIC development process from specification, RTL… more
- Palo Alto Networks (Santa Clara, CA)
- …and PCB layout rules: perform pre- and post-route signal integrity analysis of ASIC and multi- chip -module designs + Model and analyze power delivery networks ... in-person interactions. This is why our employees generally work full time from our office with flexibility offered where...the Hardware team, you collaborate closely with Board Design, ASIC Design, PCB Layout, and Validation Test. You will… more
- Capgemini (CO)
- …You're Considering** + Develop block-level and SoC-level timing constraints, and drive full - chip STA setup and signoff for multi-corner, multi-voltage designs. + ... + Develop block and SoC timing constraints, and perform full - chip STA setup and signoff for multi-corner,...and Experience** + 10 years of professional experience in ASIC implementation and CAD methodology, with a strong preference… more
- Google (Sunnyvale, CA)
- …equivalent practical experience. + 7 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification, full ... and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and full - chip static timing topics, including clocking, timing exceptions, time… more
- Google (Mountain View, CA)
- …ARM, x86, RISC-V, etc.) and Internet Protocols (IPs) used in System on a Chip (SoC) designs. + Experience with C/C++. Preferred qualifications: + Master's degree or ... and development for software layers found in Application-specific integrated circuit ( ASIC ) (eg, boot, drivers, embedded firmware, libraries, and API for… more
- Micron Technology, Inc. (Richardson, TX)
- …the DDR or LPDDR design is based on the gate-level design only while the Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) ... HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via).… more
- quadric.io, Inc (Burlingame, CA)
- …to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of ... Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: + BS/MS or Ph.D.… more
- Huntington Ingalls Industries (Roanoke, VA)
- Requisition Number: 19472 Required Travel: 0 - 10% Employment Type: Full Time/Salaried/Exempt Anticipated Salary Range: - $135,000.00 Security Clearance: Ability to ... Obtain Level of Experience: Senior This opportunity resides with Warfare Systems (WS), a...and vulnerabilities in the gate-level netlists of FPGA and ASIC designs. Candidates for this position will help lead… more