- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop ... this role, you'll develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy … more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and ... You will play a critical role in defining cross-domain timing constraints , validating IO timing ...equivalent experience). + 6+ years of experience in static timing analysis, methodology , or constraint development. +… more
- NVIDIA (Santa Clara, CA)
- … including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of ... next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our...and power/area/congestions/yield/etc. + Work on all aspects of DFT/Test timing such as timing constraints ,… more
- NVIDIA (Santa Clara, CA)
- …driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints , timing and power convergence, and ... multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology ... Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints … more
- NVIDIA (Santa Clara, CA)
- …chip level. + Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints , driving timing and power ... ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology ...in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- …and convergence of high-performance designs. + You will be responsible for all aspects of timing including setting up timing constraints , timing analysis ... timing closure of high-speed designs. + Strong background and experience in timing constraints generation, clocking, process variations and signal integrity +… more
- Capgemini (CO)
- **About the Job You're Considering** + Develop block-level and SoC-level timing constraints , and drive full-chip STA setup and signoff for multi-corner, ... failures. **Your Role** + Develop block and SoC timing constraints , and perform full-chip STA setup...methodology , with a strong preference for experience in timing closure of high-performance designs. + Proven expertise in… more
- Cisco (San Jose, CA)
- …, performance, and power requirements. * Contribute to full chip integration and timing methodology /analysis. * Develop and analyze functional coverage. * Help ... define, evolve, and support our design methodology . * Collaborate with the verification team to address...or System Verilog programming skills * Experience with simulators/synthesis/static timing constraints and related tools (eg, VCS,… more
- Palo Alto Networks (Santa Clara, CA)
- …like setup/hold constraints and delay sources. + **Mentor** junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC ... the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or… more
- Ford Motor Company (Dearborn, MI)
- …workforce and time calculation. + Responsible for defining and managing the technical, timing and budget of multiple projects + Document and track enablers and ... teams to successfully complete projects within time & resource constraints + Track project progress & report effectively on...blockers & changes to customer as well as internal senior management + Track project costs & drive cost… more