- Qualcomm (San Diego, CA)
- …for the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills ... of STA features and Timing concepts. + 2-6 years of experience in Signoff Timing of SoCs at either top-level or block-level. * 2-6 years of experience with… more
- Qualcomm (Austin, TX)
- …for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- SpaceX (Irvine, CA)
- …Bachelor's degree in electrical engineering, computer engineering or computer science + Experience in static timing analysis and/or timing closure of ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer...+ Experience in industry standard STA and Noise/Signal integrity analysis tools + Experience in clock jitter simulation and… more
- Google (Sunnyvale, CA)
- …full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... + 10 years of experience in the domain of static timing analysis . + Experience...development and support, as well as chip implementation and timing signoff execution. + Develop, support and… more
- Google (San Diego, CA)
- …. + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff process corners, derates, uncertainties ... + Experience with ASIC design flows and methodology of static timing analysis . + Effective...full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip… more
- SpaceX (Bastrop, TX)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- SpaceX (Sunnyvale, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- Meta (Austin, TX)
- …experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip ... for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and Hierarchical Clock Domain… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …higher) in Computer/Electrical Engineering + Strong knowledge of Digital Design Fundamentals and Static Timing Analysis + Prior experience with IC digital ... implementation flows - Synthesis, Place and Route, IR Drop, Timing Signoff + Prior experience with Cadence tools (Genus, Innovus, Conformal, Tempus, Modus,… more
- Google (Sunnyvale, CA)
- …design, physical design flows, and methodologies including synthesis, place and route, Static Timing Analysis (STA), formal verification, Change Data ... Capture (CDC), and power analysis . + Experience in IP integration (eg, Phase Lock...distribution and optimize related quality of results (ie, power, timing , area). You will perform technical evaluations of EDA… more
- Qualcomm (San Diego, CA)
- …> GPU ASICS Engineering **General Summary:** **Preferred Qualifications:** + Experience in static timing analysis , constraints and other physical ... using TCL and preferably Perl/Python as well. **Responsibilities** **:** + Timing analysis , validation and debug across multi-mode, multi-voltage domain… more
- Cisco (San Jose, CA)
- …- Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis with Test Constraint signoff ownership a plus.. * ... Past experience with Post silicon validation using DFT patterns and product engineering. * Have participated in multiple tapeouts and silicon bringup activities. * Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will… more