- Amazon (Sunnyvale, CA)
- …engineering groups including design, verification, backend, test, reliability and more. As part of the SOC DFT team, you will: - Develop and implement DFT ... a Sr. DFT Engineer. - Top level DFT architecture definition experience. - Scan insertion...DFT logic design. - Experience in Chip level DFT verification methodology and flow. - Perform SOC… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test ( MBIST ) and automatic test pattern ... impact on the world of technology. Looking for Lead SoC /ASIC Digital Design Engineer with experience in Design for...to silicon debug + Should possess intimate knowledge of DFT insertion flows + Basic scan chain… more
- SpaceX (Sunnyvale, CA)
- …tools (Synopsys DC, Primetime or equivalent) + Experience with clock domain crossings, DFT / Scan / MBIST /LBIST and understanding of their impact on synthesis, ... SOC /ASIC Synthesis & Front-End STA Engineer (Silicon Engineering)...Work closely with chip architecture, design verification, physical design, DFT , and power teams to achieve tapeout success on… more
- SpaceX (Redmond, WA)
- …+ Familiar with CMOS analog circuit and physical design + Knowledge of DFT / Scan / MBIST /LBIST and understanding of their impact on physical design ... Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) at SpaceX...ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- NVIDIA (Santa Clara, CA)
- …out from the crowd: + Understanding of DFT insertion techniques including SCAN , ATPG, MBIST , and IOBIST With competitive salaries and a generous benefits ... program solutions for the next generation of GPUs and SOC + ATE test program development includes constructing or...teams including IO design, PLL design, Product Development Engineering, DFT , and IC design to efficiently debug any product… more