- SpaceX (Irvine, CA)
- Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING ...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $160,000.00 - $220,000.00/per year Your actual level and… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... to make this possible, with the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Bastrop, TX)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... to make this possible, with the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering) Irvine,... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- MetaOption, LLC (Milpitas, CA)
- Sr . Front-End ASIC Design Engineer Candidate needs SoC / ASIC experience working hands on currently, with non-off the shelf designs. - Compute (ie, CPUs), ... IO (PCIe, Ethernet, etc.) are useful experience. Description We are seeking a Front-End SoC / ASIC Design Engineer for our SoC business unit. Responsibilities… more
- Amazon (Austin, TX)
- …implementing robust integration methodologies - Have deep expertise in high-performance SOC design, including clock/reset architecture, timing closure, and CDC ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...job responsibilities - Lead and grow a team of SOC integration engineers responsible for critical deliverables in our… more
- NVIDIA (Santa Clara, CA)
- …plans for NVIDIA's next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance ... experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and … more
- Amazon (San Diego, CA)
- …role you will: . Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets. . Define, ... configure and integration SoC Subsystems . Contribute to the SoC ...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... to design and implement the world's leading GPU and SoC 's. With the System- ASIC team, you will...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- Amazon (Austin, TX)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing . Analyze simulation results, identify and ... Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
- Amazon (Austin, TX)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
- Amazon (Austin, TX)
- …Bandwidth Memory (HBM) DRAM interface and memory stack testing, including training of the SOC phy to DRAM base die, stretching beyond JEDEC specs to gain maximum ... how to glean quality of connection from eye diagrams, timing margin etc. You will also work with the...building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind,… more
- Qualcomm (Santa Clara, CA)
- …volume chip production for at least one product cycle is preferred **Keywords** : ASIC ; SOC ; Low Power; Power estimates; Power Intent; Power Implementation; WiFi ... Technology team you will be working on WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/Implementation, power estimates and power… more
- L3Harris (Camden, NJ)
- …land, sea and cyber domains in the interest of national security. Job Title: Sr ASIC /FPGA VHDL Design Engineer Job Code: 22429 Job Location: Camden, ... Friday off Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff...+ Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA) + Perform RTL quality using: Lint,… more
- Qualcomm (Santa Clara, CA)
- …at connectivity module level, and chip level modes. You will assist with the timing closure of your designs. You will make regular contributions to the overall ... Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience....Significant contributions in the bring-up of at least one SOC . + Experience on at least two SoC… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …We are a great and passionate engineering team building the next Palladium Emulation ASIC and system at Cadence Design System. Palladium has been the leader in the ... team to facilitate logic changes and improved / drive timing to closure. + The position will interact with...computer engineering with a minimum of 10 years of ASIC Design experience OR MS with a minimum of… more
- Qualcomm (Folsom, CA)
- …degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree ... in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Hardware Design Engineer for our Tegra group! NVIDIA is seeking passionate Senior Hardware Design Engineers to architect, design ... and verify the world's leading SoC 's and GPU's. This position offers the opportunity to...architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. What… more