- Amazon (Portland, OR)
- …AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design - STA Engineer to continue to innovate on behalf ... Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC . * Streamlining the timing signoff criterions, timing analysis methodologies and flows.… more
- Amazon (Sunnyvale, CA)
- …AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design - STA Engineer to continue to innovate on behalf ... STA and Signoff for a complex, multi-clock, multi-voltage SoC . * Streamlining the timing signoff criterions, timing analysis...& Route and other local/remote teams to address the design challenges in the context of timing sign-off. *… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC /ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . SOC /ASIC PHYSICAL DESIGN ENGINEER...weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your… more
- SpaceX (Bastrop, TX)
- Sr . SOC /ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . SOC /ASIC PHYSICAL DESIGN ENGINEER...and fix signoff closure issues in static timing analysis ( STA ), noise, logic equivalency, physical verification, electromigration and voltage… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer. In this highly visible role, you will be ... products. Responsibilities Include: + Develop and validate timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using… more
- Amazon (Austin, TX)
- …member of the Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll provide leadership ... possible today. Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test (DFT) architectures * Work with block designers to… more
- Google (Fremont, CA)
- …qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/ SoC ) design , with a focus on both digital logic ... Senior Silicon Pre-to-Post Validation Lead, Raxium _corporate_fare_ Google...experience. + 10 years of experience in analog circuit design , including simulation and verification. + Experience working with… more
- L3Harris (Camden, NJ)
- …and cyber domains in the interest of national security. Job Title: ASIC/FPGA Design Engineer (SMES) Job Code: 29446 Job Location: Camden, NJ Schedule: 9/80 Regular ... Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part...Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for… more
- NVIDIA (Santa Clara, CA)
- …years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence...cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd:… more