- Google (San Diego, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis . + Effective skills with scripting languages ... Google (https://careers.google.com/benefits/) . + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff… more
- Qualcomm (San Diego, CA)
- …Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define and ... for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge internal and EDA technologies in… more
- Google (Sunnyvale, CA)
- … (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk. Preferred qualifications: + 10 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Amazon (Cupertino, CA)
- …possible today. Key job responsibilities * Develop & maintain flows for block and full-chip level static timing analysis * Write, debug & validate timing ... We are seeking an experienced Sr. Physical Design STA Engineer to build the next generation of our cloud...for blocks and full-chip. * Run Static Timing Analysis and give frequent feedback to… more
- Meta (Austin, TX)
- …experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and… more
- SpaceX (Irvine, CA)
- …Bachelor's degree in electrical engineering, computer engineering or computer science + Experience in static timing analysis and/or timing closure of ... critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/ Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design… more
- Meta (Austin, TX)
- … timing analysis , SI noise analysis 13. Experience with running Static Timing Analysis for full chip using DMSA 14. Knowledge of front-end and ... experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Westford, MA)
- … tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon...be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You ... be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing … more
- Qualcomm (Austin, TX)
- …setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- MetaOption, LLC (Milpitas, CA)
- …and internal teams to ensure successful ASIC tapeouts. Key Responsibilities: o Perform pre-layout Static Timing Analysis (STA) to validate feasibility and ... Physical Design Engineer Looking for someone with a wide range...layouts. o Experience with power analysis (PrimePower/Redhawk), Static Timing Analysis (Primetime), and… more
- Northrop Grumman (Dulles, VA)
- …FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis , and power analysis + US Citizen ... they're making history. We have openings for a **FPGA/ASIC Engineer ** to join our team of qualified, diverse individuals...such as RTL/gate level simulation, synthesis, place and route, static timing analysis , and power… more
- Micron Technology, Inc. (Richardson, TX)
- …expertise in design optimization for performance and low power consumption, including UPF, static timing analysis , synthesis design constraints, and closing ... the industry. **Position Overview:** As a **Principal HBM SOC Design and Integration Engineer ** , you will design and develop next-generation HBM DRAM products. You… more
- Micron Technology, Inc. (Richardson, TX)
- …for performance and low power consumption and how to use UPF. + Good knowledge of static timing analysis , synthesis design constraints, and how to close ... enrich life. As an HBM SOC Design and Integration Engineer , you will be responsible for the design &...developing RTL, integrating IP, testing code, debugging failures, running static checks and resolving issues identified by static… more
- Meta (Sunnyvale, CA)
- …designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis , IR drop, EM, and physical ... and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical...H-Tree, and clock power reduction techniques. 21. Knowledge of static timing analysis and concepts,… more
- Micron Technology, Inc. (Richardson, TX)
- …Place and Route, Power Grid, Clock Tree Synthesis, Constraint Development with RTL engineers, Static Timing Analysis for Partition Level and Full Chip Level ... the industry! **Position Overview:** Micron is hiring a Staff Engineer - HBM SOC Physical Design! You will be...1+ years of experience of Synthesis Design Constraints and Static Timing Analysis . **Preferred Qualifications:**… more
- Meta (Sunnyvale, CA)
- …19. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 20. 4 Static timing analysis and verification at different PVT corner 21. ... to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization… more
- Micron Technology, Inc. (Dallas, TX)
- …for performance and low power consumption and how to use UPF. + Good knowledge of static timing analysis , synthesis design constraints, and how to close ... life. As a MTS | DMTS HBM SOC Design Engineer , you will be responsible for the design &...developing RTL, integrating IP, testing code, debugging failures, running static checks and resolving issues identified by static… more