- Qualcomm (Santa Clara, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop ... timing constraints, drive implementation of the designs to meet...STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in… more
- Northrop Grumman (Morrisville, NC)
- …career. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly qualified, diverse ... Secret clearance.** **Roles and Responsibilities:** + Responsible for static timing analysis on digital designs to ensure timing... timing analysis on digital designs to ensure timing requirements are met + Identify timing … more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem ... you'll be doing: + You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and… more
- CACI International (Denver, CO)
- Network Timing Engineer Job Category: Information Technology Time Type: Full time Minimum Clearance Required to Start: TS/SCI with Polygraph Employee Type: ... on an ongoing basis. **Opportunity:** We are seeking an experienced Network Engineer to design, implement, and maintain a CAN/LAN environment hosting complex command… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and ... I/O interface modeling to architect and deploy robust timing signoff practices across high-performance SoCs. You will play...You will play a critical role in defining cross-domain timing constraints, validating IO timing integrity, and… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- Meta (Austin, TX)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the...budgets for the various partition blocks 2. Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints Apply (https://jobs.cisco.com/jobs/Login?projectId=1439367) + Location:San Jose, California, US + Area of ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering ... this role, you'll develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional...(eg, PrimeTime, SNPS TCM ) and debug anomalies in timing reports. + Support tapeout-quality STA environments that are… more
- Google (Sunnyvale, CA)
- …related field, or equivalent practical experience. + 2 years of experience in static timing analysis. + Experience in Primetime or Tempus Tcl scripting and static ... timing analysis debug and problem solving. + Experience in sub chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, ... GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You...+ You will be responsible for all aspects of timing including setting up timing constraints, … more
- NVIDIA (Westford, MA)
- …inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, ... be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at...from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and… more
- Cisco (San Jose, CA)
- ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US + ... from concept to first customer shipments **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- NVIDIA (Austin, TX)
- …machine learning, and novel algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale and high accuracy gate-level ... power, timing , parasitic, and noise analysis. A deep understanding of...optimize methods to improve the accuracy and capacity of timing , power, and noise models used within a suite… more
- Meta (Austin, TX)
- …in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for ... data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced optimization… more
- State of Georgia (Dekalb County, GA)
- D7- Pro Civil Engineer 5 District Traffic Operations Manager (PG:O) Georgia - Dekalb - Chamblee ... Job Sign Up for Job Alerts D7- Pro Civil Engineer 5 District Traffic Operation Mgr Pay Grade O...but are not limited to traffic engineering studies, signal timing /phasing studies, computerized monitoring and control of signal operation… more
- Microsoft Corporation (Santa Clara, CA)
- …superior performance compared to CPU-based alternatives We're seeking a Physical Design Engineer . As part of our DPU silicon team in Santa Clara, you'll ... ownership of important designs and drive them tapeout, meeting all timing , physical, electrical, and manufacturing requirements: + Perform early design exploration… more
- WSP USA (Fort Myers, FL)
- WSP is currently initiating a search for a **Senior Arterial Operations Engineer ** to work on a client site out of **Bradenton, FL** . The Senior Arterial Operations ... Engineer will work from the client building. Scheduled shift...+ Provide guidance to develop, update, and maintain signal timing changes. + Implement or provide guidance to Lead… more