- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Austin, TX)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Austin, TX)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Micron Technology, Inc. (Minneapolis, MN)
- …strong foundation in ASIC verification . **Responsibilities** + Work with UVM -based SystemVerilog testbenches to verify ASIC functionality. + Collaborate with ... learn, communicate and advance faster than ever. **Department Introduction** Micron's ASIC Design Verification team ensures the functionality and quality of… more
- Microsoft Corporation (Redmond, WA)
- … verification plans, develop SystemVerilog testbenches using Universal Verification Methodology ( UVM ), and collaborate closely with firmware, software, ... that shape the future for millions worldwide. As a Design Verification Engineer in Azure Core, you...technical leadership, mentor engineers, and deepen your expertise in UVM . As part of a focused verification … more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Amazon (Sunnyvale, CA)
- … engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define ... legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in… more
- Capgemini (Seattle, WA)
- …Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in design ... **Job Description:** We are seeking a SoC Design Verification Engineer to join our...+ 8 to 10 years of hands-on experience with SystemVerilog and UVM methodology. + Proficiency in… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven … more
- Northrop Grumman (Annapolis Junction, MD)
- …The Systems Engineering Integration & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and develop these technologies ... verification processes. **Role And Responsibilities:** The Debug and Staff Lead Design Verification Engineer will be responsible leading the verification … more
- Northrop Grumman (Annapolis Junction, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting...with Polygraph. + Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience Northrop… more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- BAE Systems (San Diego, CA)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- Amazon (Cupertino, CA)
- …- Expertise in various verification languages and tools such as SystemVerilog , UVM , Verilog, and simulation/emulation platforms - Proven track record of ... Qualifications - 8+ years of hands-on experience in ASIC/VLSI design verification , with a strong understanding of... verification , with a strong understanding of verification methodologies such as UVM , along with… more
- NVIDIA (Santa Clara, CA)
- We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... join our diverse team today! As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify...models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM . + Build… more
- Google (Mountain View, CA)
- …infrastructure IPs, interconnects, and memory subsystems. + Create and enhance constrained-random verification environments using SystemVerilog and UVM . + ... ASIC Design Verification Engineer, Devices and Services...experience with verifying digital logic at RTL level using SystemVerilog or C/C++ Experience creating and using verification… more
- Northrop Grumman (Annapolis Junction, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Familiarity with a...or PhD + Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience +… more
- L3Harris (Rochester, NY)
- …with system requirements and specifications. + Develop self-checking test benches for FPGA design verification and validation using SystemVerilog . + Develop ... Programming(C++, JAVA). + Proven proficiency in FPGA/ASIC verification using SystemVerilog . + Working knowledge of UVM /OVM methodology. + Experience with… more
- Amazon (Sunnyvale, CA)
- … verification , preferably in communication systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab model : development ... . Participate in the validation of ASIC implementations in Verilog/ SystemVerilog . Run formal verification of complex...and communication systems team and participate in system level verification using test benches constructed using UVM ,… more