- Google (Portland, OR)
- … memory subsystem design . + 10 years of experience in high-performance CPU , cache subsystem or AI accelerator logic/RTL design including ... . + Lead and manage a team of design engineers working on CPU , cache subsystem , or AI accelerator design and integration into SoC, emphasizing… more
- Microsoft Corporation (Hillsboro, OR)
- …+ 4+ years logic design experience as a part of either CPU , Cache , Fabric, Compute Tile, Digital Power Management, PCMs, Debug, Peripherals and/or ... Design Team, contributing to micro-architecture implementation, RTL coding, IP and subsystem development, and SoC integration, along with design quality… more