- Meta (Austin, TX)
- …in support of our industry leading virtual and augmented reality systems.As a Design Verification Engineer (DVEs), you will be a key contributor in planning, ... reviewing and executing our front-end verification efforts at the IP and sub-system...leading virtual and augmented reality systems. **Required Skills:** Design Verification Engineer Responsibilities: 1. Self sufficient and… more
- SpaceX (Irvine, CA)
- SoC/ASIC Physical Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... with the ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
- SpaceX (Irvine, CA)
- ASIC Emulation Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring ... with the ultimate goal of enabling human life on Mars. ASIC EMULATION VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
- Capgemini (Santa Clara, CA)
- …Canada by Capgemini **Job description:** We are looking for Senior Design Verification Engineer **Key responsibilities:** + Proficient in System Verilog ... verification using UVM experience + Familiarity with C/C model integration in verification environments + Debug skills at IP and subsystem level **Required… more
- Microsoft Corporation (San Francisco, CA)
- …designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property ( IP ) and system on chip (SoC) ... augmented reality. We are looking for a **Principal Design Verification Engineer ** to work in the dynamic...as Python or Perl. + Hands-on experience in Formal property verification , formal verification of… more
- Meta (Sunnyvale, CA)
- …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a ... multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...verification plans for each of the different core IP . 2. Define and track detailed test plans for… more
- Meta (Sunnyvale, CA)
- …the entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... for multiple state of the art graphics IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with cross-functional leads, including… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and implementation of the world's leading SoC's and GPU's. This position ... computing. What you'll be doing: + As a Senior Verification Engineer at NVIDIA, you will be...code using Object Oriented Programming principles. + Proficient in verification of design IP with SystemVerilog, advanced… more
- Microsoft Corporation (Mountain View, CA)
- …for a **Senior Design Verification Engineer ** to work on leading-edge Intellectual Property ( IP ) development as part of the Semi-Custom and Central ... the development of custom Intellectual Property ( IP ) components. + Define pre-Silicon verification (simulation/emulation/formal proofs/field-programmable… more
- Microsoft Corporation (Mountain View, CA)
- …every day. **Responsibilities** + Own and deliver on design verification of complex Intellectual Property ( IP ) or Subsystem or System on Chips(SoC) level ... efficient manner. We are looking for a **Principal Design Verification Engineer ** to work in the dynamic... IP level, subsystem level and SoC level verification environments; and verification IP … more
- Capgemini (Santa Clara, CA)
- … * System Verilog assertions experience * Familiarity with C/C model integration in verification environments * Debug skills at IP and subsystem level Good to ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Meta_Design Verification Engineer_ **Location:** _CA-Santa Clara_… more
- The Boeing Company (Tukwila, WA)
- … processes, ensuring seamless integration and functionality within satellite systems. The FPGA Verification Engineer is integral to our commitment to quality and ... Space, Intelligence & Weapons Systems has an exciting opportunity for FPGA** ** Verification Engineers at Experienced, Lead and Senior levels** **to join us as… more
- Renesas (Edinburgh, IN)
- Principal Verification Engineer Job Description **Job Purpose:** The purpose of this job is to guarantee specification compliance of digital or mixed signal ... strategy for digital and mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM… more
- Qualcomm (San Diego, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... in verifying complex SOC or SOC subsystems + Experience with caches and DDR memory protocol verification + Experience with using memory verification VIP's +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Verification Engineer for our Tegra group! NVIDIA is seeking outstanding Senior Verification Engineers to verify the design ... degrees (MS, PhD) a plus. + 4+ years of experience in ASIC verification -related fields at IP and SOC level. + Experience in writing UVM testbench from scratch… more
- Meta (Sunnyvale, CA)
- …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a ... of distance, and even the rules of physics. **Required Skills:** Design Verification Engineer , Silicon Engineering (University Grad) Responsibilities: 1. Define… more
- Capgemini (Austin, TX)
- …are looking for Senior DV Engineer who will define and write IP verification plans based on requirements documents (industry standards, product requirements, ... **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification Engineer_ **Location:** _TX-Austin_ **Requisition… more
- Amazon (Sunnyvale, CA)
- Description As a Design Verification Engineer at Amazon, you will be part of an advanced engineering and research team that is building world class hardware for ... languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or… more
- BAE Systems (Manchester, NH)
- …your leadership skills while leading small to medium sized DV teams + Create reusable Verification IP to be shared across the organization; + Drive changes to ... VHDL + FPGA Design Experience + Experience creating reusable Verification IP . + Experience leading small to...available based on position level and/or job specifics. **Design Verification Engineer - FPGA - (Sign-on Bonus)**… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Verification Engineer to join our Display Team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU ... on UVM methodology. + Monitor the overall health of IP by defining and tracking verification metrics....health of IP by defining and tracking verification metrics. Analyze functional/code coverage and work with design… more