- Honeywell (Clearwater, FL)
- …+ Build Requirements, Design and Simulation + Conduct Code Synthesis + Static Timing Analysis/Timing Closure + Integration and Test Support + Provide Customer Support ... + Prepare Documentation + Mentor junior engineers + ASIC/FPGA design using Verilog/VHDL and/or verification using System Verilog/UVM + Good VHDL or Verilog working knowledge + Some travel within US/International may be required (<10%) US PERSON REQUIREMENTS… more