- Google (Sunnyvale, CA)
- …tool workflows in semiconductor environments. + Experience developing and supporting ASIC physical design flows and methodologies in process nodes. + Experience ... and analyzing trends. + Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC integration and signoff, IP integration, chip… more
- Microsoft Corporation (Santa Clara, CA)
- We are looking for a ** Physical Design Methodology Engineer** . As part of our DPU silicon team, you will help lead the way for our cutting-edge ASICs, ... supporting world-class silicon Physical Design . **Responsibilities** + Ownership of flows...+ 2+ years of experience on scripting (TCL/Perl) and/or flow automation **Other requirements:** + Ability to meet Microsoft,… more
- NVIDIA (Santa Clara, CA)
- …devices for high-speed optical interconnect and sensing applications. + Developing physical design methodologies for implementation of graphics processors and ... and creative solutions to the state of the art physical design problems that are needed for...are needed for NVIDIA chips. + Participate in developing flow and tool methodologies for chip floorplan, waveguide routing,… more
- NVIDIA (Santa Clara, CA)
- …our team with varied strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. + ... and creative solutions to the state of the art physical design problems that are needed for...are needed for NVIDIA chips. + Participate in developing flow and tool methodologies for chip floorplan, power and… more
- NVIDIA (Santa Clara, CA)
- …+ BS or MS (or equivalent experience) + 8+ years of experience in logic design implementation and/or physical design implementation + Deep understanding of ... and relative area, timing, and power trade-offs + Strong understanding of physical design implementation eg: physical synthesis, placement, routing,… more
- NVIDIA (Santa Clara, CA)
- …for NVIDIA's front-end ASIC software including RTL synthesis, equivalence checking, and early physical design and methodology for all of NVIDIA's ... algorithms, data structures, testing + Familiarity with Verilog and ASIC and physical design along with experience in commercial EDA tools + Strong proficiency… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPUs, GPUs, SoCs… more
- Qualcomm (Santa Clara, CA)
- …flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows ... envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build...and release new features in our high-performance place-and-route CAD flow + Architect and recommend methodology improvements… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and Route, timing and power signoff. + Understanding and proliferating Cadence flow solutions in the areas of 3DIC implementation and ML/AI based implementation ... Primetime. + Working closely with R&D on tools and methodology improvements + Create and contribute technical content for...+ Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We ... & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow ...- Should be able to work closely with IP Design teams and Backend Physical Design… more
- Microsoft Corporation (Mountain View, CA)
- …constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology (UVM) components ... servers, clients, and augmented reality. We are looking for a **Senior Design Verification Engineer** to work on leading-edge Intellectual Property (IP) development… more
- Qualcomm (Santa Clara, CA)
- …and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology . Involve in developing automation to improve ... Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from… more
- Siemens Digital Industries Software (Fremont, CA)
- …line such as Placement, Clock Tree Synthesis, Optimization and Routing. Work on physical design activities for advanced technology nodes. Assess power domain ... exempt employees)._ **Duties:** Work on defining Place and Route flow and methodology for designs from networking,...the area of Very Large Scale Integration [VLSI] / Physical design implementation. Work with Digital Implementation… more
- Microsoft Corporation (Mountain View, CA)
- …equivalence checking tools, flows, and methods to our rapidly expanding RTL and physical design teams located across various sites within the Microsoft silicon ... flow systems + Perform detailed debug/analysis to guide the RTL and physical design teams across Microsoft's silicon portfolio in addressing and solving… more
- NVIDIA (Santa Clara, CA)
- …or Computer Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis ... of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg...and clock controls in DFT modes. + Experience in methodology or flow development. NVIDIA is widely… more
- SpaceX (Sunnyvale, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff +... and timing closure + Deep understanding of ASIC design flow , top-down and bottom-up design… more
- ManpowerGroup (San Jose, CA)
- …engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design , verification, physical design , emulation and firmware. We use ... **The Work:** The ideal candidate can help along the design flow to establish synthesis runs with...(Static Timing Analysis) and PrimeTime and related timing constraints methodology and SDC constraints language + A minimum of… more
- Amazon (Sunnyvale, CA)
- …related to DFT logic design . - Experience in Chip level DFT verification methodology and flow . - Perform SOC/IP DFT Gate-level simulations. - Static timing ... at edge. Work hard. Have Fun. Make history. At Amazon, DFT ( Design -for-Testability) is a multi-faceted job that involves architecture definition, logic design… more
- Medtronic (Santa Clara, CA)
- …and drafting), metal machining and materials, injection molding and polymer flow /behavior, design for machining and over-molding, finite element analysis ... performed at all levels of total system product to include concept, design , fabrication, test, installation, operation, maintenance and disposal. + Maintains and… more
- Lucile Packard Children's Hospital Stanford (Palo Alto, CA)
- …of equity. + Demonstrate financial acumen and a deep understanding of payment methodology , funds flow , physician incentives, and cost control techniques. + ... clinical programs; and co-chairing or otherwise participating in the determination of funds flow between SMCH and the School of Medicine. As the Senior Associate… more