• RTL Senior Principal

    Cadence Design Systems, Inc. (San Jose, CA)
    …development progress and status. This includes but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design, debug and ... team of engineers that can learn and improve existing digital flows. The candidate will primarily be responsible for...scripting and developing flows at all phases of the digital design and functional verification. It is further expected… more
    Cadence Design Systems, Inc. (03/01/24)
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  • Senior RTL to GDS Principal

    Cadence Design Systems, Inc. (San Jose, CA)
    …in the field of artificial intelligence and machine learning. As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work ... enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales… more
    Cadence Design Systems, Inc. (04/19/24)
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  • Senior RTL to GDS Principal

    Cadence Design Systems, Inc. (San Jose, CA)
    …Provide technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and ... or related field8+ years of design/EDA experienceStrong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is… more
    Cadence Design Systems, Inc. (04/27/24)
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  • CPU Micro-architect/ RTL Designer

    Qualcomm (Santa Clara, CA)
    …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties and Responsibilities:** ... the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As… more
    Qualcomm (04/10/24)
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  • Senior Principal ASIC Design…

    BAE Systems (San Jose, CA)
    …Systems. We are seeking a very senior level engineer to: + Design and RTL coding of high-speed digital circuits on ASIC/FPGAs from concept to production. + ... Other incentives may be available based on position level and/or job specifics. ** Senior Principal ASIC Design Engineer (Hybrid)** **95186BR** EEO Career Site… more
    BAE Systems (04/13/24)
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  • Senior Principal Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …Responsibilities include hardware architecture and micro-architecture definition, as well as RTL design to achieve high performance and low power. Familiarity with ... for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs… more
    Cadence Design Systems, Inc. (04/11/24)
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  • Digital Design Engineer (Staff)

    Qualcomm (Santa Clara, CA)
    …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties & Responsibilities:** ... all. As a Qualcomm ASIC Engineer, you will define, model, design ( digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC)… more
    Qualcomm (04/20/24)
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  • Sr. Digital Design Engineer

    Integense (San Jose, CA)
    …to our customers. We are expanding and looking for a Senior / Principal Member of Technical Staff, Digital Design. This is an exciting opportunity to ... what matters. A true expert in all aspects of digital design, you enjoy problem-solving and balancing the many...Experienced in all Front and Back End activities - RTL , Verification, Synthesis, STA, DFT, ATPG, etc. + Adept… more
    Integense (03/27/24)
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  • Mixed Signal IP - Senior Program Manager

    Cadence Design Systems, Inc. (San Jose, CA)
    …develop leaders and innovators who want to make an impact on the world of technology. Senior Principal Program Manager We are looking for a Senior Technical ... of end-to-end design flow and tools for both analog and digital design from Architecture (schematics and RTL ) to GDS + MSEE preferred Key competencies + critical… more
    Cadence Design Systems, Inc. (02/27/24)
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  • Senior Physical Design Applications…

    Cadence Design Systems, Inc. (San Jose, CA)
    …experience with ASIC digital implementation flows and EDA tools is required, RTL to GDSII ; Experience with advanced nodes (7nm and below) preferred. + Must ... who want to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for… more
    Cadence Design Systems, Inc. (04/13/24)
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  • Senior DFT Engineer

    Qualcomm (San Jose, CA)
    …Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** The Digital ASIC Design Team is currently seeking candidates who will be ... Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like...and team work skills and good English is required ** Principal Duties & Responsibilities:** + The person hired in… more
    Qualcomm (04/18/24)
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