- Cadence Design Systems, Inc. (San Jose, CA)
- …innovators who want to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical ... support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving challenges in meeting power, performance and area (PPA) in vertical markets such as datacenter, ML/AI, networking and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …technology. We are excited to welcome highly talented hardware designers and application engineers to join our Cadence North America Field Applications Team. Working ... or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …technology. We are excited to welcome highly talented hardware designers and application engineers to join our Cadence North America Field Applications Team. Working ... at Cadence means working alongside the industry's brightest people and innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, from helping build the… more
- Microsoft Corporation (Mountain View, CA)
- …years of experience in hardware design. + 6+ years of experience in RTL -to- GDS tasks such as floorplanning, bump planning, synthesis, timing closure, ... servers, clients, and augmented reality. We are looking for a ** Principal Physical Design Engineer** to work on industry-leading, high-speed, mixed-signal interface… more
- Microsoft Corporation (Mountain View, CA)
- …the complete spectrum including Design for Testability (DFT), full Register Transfer Level ( RTL ) design ( GDS )Graphic Data Stream (RTL2GDS), and signoff. If you ... most ambitious chips in the industry. The Physical Design team is looking for Principal Static Timing Analysis (STA) Engineer to join us as we continue to build… more
- Qualcomm (Santa Clara, CA)
- …verification or similarly for custom circuit design/layout flow. * Utilizes tools/applications (eg, RTL to GDS Flow, Virtuoso) to execute and enable advanced ... quality check such as lint, CDC and low power rule checks . RTL -level and gate-level vector-based power analysis **Minimum Qualifications:** * Bachelor's degree in… more