- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... We are looking for SOC Design Engineer! The complexity of...complex GPU and Tegra chips and interface, directly with unit- level ASIC, Physical Design , CAD, Package … more
- SpaceX (Irvine, CA)
- SOC Physical Design STA/Timing Engineer (Silicon...Debug and drive fixing of constraint correlation issues between top and block level + Develop clock ... this possible, with the ultimate goal of enabling human life on Mars. SOC /ASIC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Google (Sunnyvale, CA)
- …data centers affecting millions of Google users. You will join a team working on SoC - level RTL design for data center accelerators. In this role you ... silicon, emulation, FPGA validation and debug, functional verification, physical design , and DFT methodologies. + Experience with SOC.... + Own the planning, creation, and delivery of top - level RTL/deliverables for ASIC and SOC… more
- P 11 Security, Inc. (Colorado Springs, CO)
- Security Operation Center ( SOC ) Analyst Lead Colorado Springs, CO (http://maps.google.com/maps?q=N/A+Colorado+Springs+CO+USA+80912) Description Lead SOC ... Analyst's primary function is to develop, implement, and evaluate a SOC teams' ability to provide comprehensive Computer Network Defense and Response support through… more
- General Dynamics Information Technology (Colorado Springs, CO)
- **Req ID:** RQ166630 **Type of Requisition:** Regular **Clearance Level Must Be Able to Obtain:** Top Secret SCI + Polygraph **Public Trust/Other Required:** ... + years of related experience **US Citizenship Required:** Yes **Job Description:** Lead SOC Analyst's primary function is to develop, implement, and evaluate a … more
- SpaceX (Irvine, CA)
- …chip physical verification and work with physical design (PD) team to close design issues + Execute SOC GDSII integration, seal ring addition and tapeout ... to the foundry + Work closely with semiconductor foundries on installation, maintenance of process design kits (PDKs) for SOC physical design teams + Be the… more
- Elevance Health (Columbus, OH)
- …you a check, or ask you for payment as part of consideration for employment. **FedRAMP SOC Analyst** + Job Family: IFT > IT Security & Compliance + Type: Full time + ... Tennessee + Florida + Illinois + Georgia **Description** **FedRAMP SOC Analyst** **Location:** This position will work a hybrid...3 years experience in a support & operations or design & engineering role in any of the following… more
- SpaceX (Sunnyvale, CA)
- …and STA Signoff + Experience with power intent and upf development for block and SOC top + Familiar with formal verification and implementing functional ECOs + ... SOC /ASIC Synthesis & Front-End STA Engineer (Silicon Engineering)... and timing closure + Deep understanding of ASIC design flow, top -down and bottom-up design… more
- Leidos (San Diego, CA)
- …IP and DFT configurations + Provide technical guidance and subcontractor oversight throughout SoC design process to include, supervising design activities ... (LInC) at Leidos currently has an opening for a mid- level hardware design engineer to support a...include ASICs, FPGAs, DSPs, data converters + Familiarity with SoC design flow to include RTL, DFT,… more
- The Boeing Company (Huntington Beach, CA)
- … Design Automation (EDA) tools and methodologies for digital ASIC/FPGA/ SoC design and verification (eg Synopsys, Cadence) **Preferred Qualifications ... (Virtuoso suite and Spectre simulator products) + Experience working on large-scale SoC design teams. + Experience developing Mixed-Signal circuits in… more
- The Boeing Company (Tukwila, WA)
- …(Virtuoso suite and Spectre simulator products) + Experience working on large-scale SoC design teams. + Experience developing Mixed-Signal circuits in ... actively hiring an **Analog Mixed Signal Integrated Circuit (IC) Design Engineer (Mid- Level or Lead),** who has...Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include… more
- NVIDIA (Hillsboro, OR)
- …CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate ... chance to build complex chips and interact directly with unit- level ASIC, Physical Design , CAD, Package ...equivalent experience + 5+ years of experience in chip design , specializing in SOC integration and … more
- Leidos (Arlington, VA)
- …(> GHz) design techniques + ARM or RISC-V embedded processor based SoC design experience + Experience with performance characteristics of analog data ... of Leidos is looking for a FPGA DSP Firmware Design Engineer to work with a multi-disciplined design...integrate DSP applications for latest System on a Chip ( SoC ) implementations such as Xilinx Zynq Ultrascale+, Intel Stratix-10,… more
- Leidos (St. Petersburg, FL)
- …(> 20GHz) design techniques * ARM or RISC-V embedded processor based SoC design experience * Proven experience in the military/aerospace hi reliability ... for a FPGA DSP Firmware Engineer to lead a design team to design , develop, simulate, and...testing. * Conduct experimental tests on latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications… more
- Leidos (Arlington, VA)
- …(> 20GHz) design techniques + ARM or RISC-V embedded processor based SoC design experience + Proven experience in the military/aerospace hi reliability ... for a FPGA DSP Firmware Engineer to lead a design team to design , develop, simulate, and...testing. + Conduct experimental tests on latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. NVIDIA is on the move and ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- Meta (Sunnyvale, CA)
- …and/or C/C++ based verification. 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. ... of detailed test plans for the different modules and top levels. 3. Implement scalable test benches including checkers,...6. Support hand-off and integration of blocks into larger SOC environments. 7. Develop and drive continuous Design… more
- Microsoft Corporation (Sunnyvale, CA)
- …experience in SOC Integration. + Experience in delivery of ASIC IPs, sub-systems and/or top level SOC RTL for 3+ tape outs. **Other Requirements** + ... with SOC Integration and Intellectual Property (IP) Design Engineers to ensure Register Transfer Level ...SOC integration challenges at subsystem and full chip level . + Experience with clock/reset design . Silicon… more
- ManpowerGroup (Phoenix, AZ)
- …in vector and vector-less modes of ASIC SoC design at different design stages from RTL to gate- level netlist. + Develop & own power grid implementation ... & implementation o Power integrity analysis at block and top level , including EM, IR & ESD...EM, IR & ESD analysis, power reduction techniques in SOC design . + Power constraints generation and… more