- SpaceX (Sunnyvale, CA)
- SOC /ASIC Synthesis & Front-End STA Engineer...+ Experience with test modes, mode merging to optimize physical design implementation and STA ... the ultimate goal of enabling human life on Mars. SOC /ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...and timing closure + Work closely with chip architecture, design verification, physical design , DFT,… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We ... STA and Signoff for a complex, multi-clock, multi-voltage SoC . - Streamlining the timing signoff criterions, timing analysis...- Should be able to work closely with IP Design teams and Backend Physical Design… more
- Qualcomm (Santa Clara, CA)
- …future for all. As a Qualcomm Hardware Engineer, you will plan, design , optimize, verify, and test electronic systems. Qualcomm Hardware Engineers collaborate with ... of Qualcomm Connectivity organization responsible for the development of SoC designs. Roles/Responsibilities: Job responsibilities include RTL Synthesis using state… more
- Google (Sunnyvale, CA)
- …that goes into our cutting-edge data centers affecting millions of Google users. As a SoC Physical Design Engineer, you will collaborate with Functional ... equivalent practical experience. + 4 years of experience with physical design flow such as floor planning,...design areas such as synthesis, place and route, STA , formal verification, or power analysis. Preferred qualifications: +… more
- ManpowerGroup (San Jose, CA)
- …engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design , verification, physical design , emulation and firmware. We use ... **We Are:** The Silicon Design group is a diverse team of world...an unparalleled time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal candidate can… more
- Qualcomm (Santa Clara, CA)
- …drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best ... should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design , and successful industry experience with deployment of IPs in large SoC… more
- Microsoft Corporation (Sunnyvale, CA)
- …+ Lead SOC implementation and integration strategies. + Collaborate with SOC Integration and Intellectual Property (IP) Design Engineers to ensure Register ... and debugging for various features at both IP and SOC levels as required. + Perform design ...Connectivity tools, CDC checkers, low power intent, linting, Synthesis, STA ). + Experience in designing for testability, debug, and… more
- Qualcomm (San Jose, CA)
- …Group, Engineering Group > ASICS Engineering **General Summary:** The Digital ASIC Design Team is currently seeking candidates who will be responsible for the ... implementation and verification of DFT/DFD ( Design for Test/ Design for Debug) techniques for...propose best compression that can be achieved for given SoC /core/block + Own and deliver scan insertion, validate equivalence… more
- NVIDIA (Santa Clara, CA)
- …experience in ASIC Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full ... plans for NVIDIA's next generation of CPU, GPU or SOC designs. + Owning STA of large...of RTL/logic design skills as well as physical design /circuit skills for timing closure. +… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block ... quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence,...timing issues, timing constraints and clocking. + Expertise in STA tools and methodologies for timing closure with a… more