- SpaceX (Irvine, CA)
- SOC Physical Design STA /Timing Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is ... this possible, with the ultimate goal of enabling human life on Mars. SOC /ASIC PHYSICAL DESIGN STA /TIMING ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Sunnyvale, CA)
- SOC /ASIC Synthesis & Front-End STA Engineer...+ Experience with test modes, mode merging to optimize physical design implementation and STA ... the ultimate goal of enabling human life on Mars. SOC /ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...and timing closure + Work closely with chip architecture, design verification, physical design , DFT,… more
- Amazon (San Diego, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We ... STA and Signoff for a complex, multi-clock, multi-voltage SoC . - Streamlining the timing signoff criterions, timing analysis...- Should be able to work closely with IP Design teams and Backend Physical Design… more
- ManpowerGroup (Phoenix, AZ)
- … Integration/ STA /Synthesis Engineer** Required Skills: + Develop and own physical design implementation of multi-hierarchy low-power designs including ... Resolve design and flow issues related to physical design , identify potential solutions, and drive...design of an end-to-end IP or integration of ASIC/ SoC design Minimum Qualifications: + Bachelor's degree… more
- Qualcomm (Austin, TX)
- …and Static Timing Analysis. **Responsibilities:** Include various aspects of physical design implementation and static timing analysis ( STA ) of DSP. Work on ... routing, STA , ECO generation and overall physical design convergence. deliverables include place and... design , or verification problems. + Own the design and verification strategies of ASICs, SoC ,… more
- Qualcomm (Santa Clara, CA)
- …future for all. As a Qualcomm Hardware Engineer, you will plan, design , optimize, verify, and test electronic systems. Qualcomm Hardware Engineers collaborate with ... of Qualcomm Connectivity organization responsible for the development of SoC designs. Roles/Responsibilities: Job responsibilities include RTL Synthesis using state… more
- ManpowerGroup (San Jose, CA)
- …engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design , verification, physical design , emulation and firmware. We use ... **We Are:** The Silicon Design group is a diverse team of world...an unparalleled time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal candidate can… more
- Qualcomm (San Diego, CA)
- …static timing analysis and power aware formal verification. + Work closely with RTL design , physical design teams to optimize area, performance and power. ... work on synthesis, timing constraints, formal verification, power analysis, STA and CLP for premium tier chips. This is...design constraints to achieve timing closure of complex soc cores. + Tabulate metrics results for QOR comparison.… more
- ManpowerGroup (Phoenix, AZ)
- **Role: Physical Design -Power Integrity Flow Development Engineer** **Location: Phoenix, AZ** **Experience: 9 years** **Job Description** + Perform comprehensive ... power analysis in vector and vector-less modes of ASIC SoC design at different design ...+ Resolve power & power integrity issues related to physical design , identify potential low power solutions,… more
- Qualcomm (San Diego, CA)
- …high performance ASIC/ SoC design flows (micro-architecture, RTL design , verification, synthesis, timing/ STA , UPF, CLP, LEC formal verification, DFT, ... This is a great opportunity to join a fast-paced SoC team responsible for development of next Generation, high...PrimeTime PX (PTPX) and work with cross-functional teams - design , implementation, and physical design … more
- Qualcomm (Austin, TX)
- …drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best ... should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design , and successful industry experience with deployment of IPs in large SoC… more
- Teradyne (North Reading, MA)
- …to ensure high quality RTL and first pass silicon success + Providing timing constraints and STA support to the Physical Design team through timing closure + ... node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne's products in many...involved in all phases of development including specification, architecture, design , verification, physical design , and… more
- Microsoft Corporation (Sunnyvale, CA)
- …+ Lead SOC implementation and integration strategies. + Collaborate with SOC Integration and Intellectual Property (IP) Design Engineers to ensure Register ... and debugging for various features at both IP and SOC levels as required. + Perform design ...Connectivity tools, CDC checkers, low power intent, linting, Synthesis, STA ). + Experience in designing for testability, debug, and… more
- Cadence Design Systems, Inc. (Austin, TX)
- …and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, synthesize RTL ... looking for an experienced RTL designer to contribute to architecture and design for next generation SoCs targeting Hyper-Scalar, Automotive, IoT and Mil-Aero… more
- Meta (Austin, TX)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... STA for the blocks and the top-level including SOC . Analyze the inter-block timing and come up with...Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design… more
- Qualcomm (San Diego, CA)
- …system-level in 5nm, 4nm and beyond (process technologies). + You will be working with physical design team (and other teams) on timing closure, CAD teams, IP ... will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level...different projects and support timing sign off for complex SOC 's. Hands on contribution for STA timing… more
- Qualcomm (San Jose, CA)
- …Group, Engineering Group > ASICS Engineering **General Summary:** The Digital ASIC Design Team is currently seeking candidates who will be responsible for the ... implementation and verification of DFT/DFD ( Design for Test/ Design for Debug) techniques for...propose best compression that can be achieved for given SoC /core/block + Own and deliver scan insertion, validate equivalence… more
- Micron Technology, Inc. (Minneapolis, MN)
- …to ensure a smooth interface between Digital and Analog circuits, project execution, and SoC integration. + Write scripts to automate design tool flows as ... Design and RTL development experience + Good knowledge of digital logic design , IP/ SoC architecture, and microarchitecture + Good knowledge of scripting using… more
- NVIDIA (Santa Clara, CA)
- …experience in ASIC Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full ... plans for NVIDIA's next generation of CPU, GPU or SOC designs. + Owning STA of large...of RTL/logic design skills as well as physical design /circuit skills for timing closure. +… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block ... quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence,...timing issues, timing constraints and clocking. + Expertise in STA tools and methodologies for timing closure with a… more