- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are ... inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and...ASIC design including RTL and logic design , physical and circuits design ,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and … more
- Amazon (Sunnyvale, CA)
- Description As a Sr. ASIC Design Engineer, you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop ... IP in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional...registers, and error handling. - Experience working closely with physical design teams to develop highly optimized… more
- SpaceX (Irvine, CA)
- Sr. ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity ... ultimate goal of enabling human life on Mars. SR. ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER...CA or Irvine, CA COMPENSATION AND BENEFITS: Pay range: ASIC Engineer/ Senior : $160,000.00 - $220,000.00/per year Your… more
- SpaceX (Irvine, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $160,000.00 - $220,000.00/per year Your ... Sr. FPGA/ ASIC Design Engineer (Silicon Engineering) at...age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... Sr. ASIC Design Engineer, DDR IP (Silicon...age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants… more
- SpaceX (Sunnyvale, CA)
- Sr. ASIC Design Verification Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- NVIDIA (Santa Clara, CA)
- … Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or ... We are now looking for a motivated Senior ASIC Engineer, Timing to join...intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs,… more
- NVIDIA (Santa Clara, CA)
- … Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or ... We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...of RTL/logic design skills as well as physical design /circuit skills for timing closure. +… more
- SpaceX (Sunnyvale, CA)
- …top-level integration of connectivity, system bus, peripherals and CPU IP + Experience in ASIC physical design and strong experience in mixed-signal IP ... Sr. SOC/ ASIC Physical Verification Engineer (Silicon Engineering)...full chip physical verification and work with physical design (PD) team to close … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- NVIDIA (Westford, MA)
- …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level,… more
- SpaceX (Irvine, CA)
- …or microcontroller control solutions for the test systems + Work closely with the FPGA/ ASIC design team and flight software team to add/improve testability and ... will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In this… more
- NVIDIA (Santa Clara, CA)
- … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you ... or Computer Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis… more
- SpaceX (Irvine, CA)
- …or DFT setup, integration and validation PREFERRED SKILLS AND EXPERIENCE: + Understanding of ASIC design flow, methodologies, physical design , and ... + Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools + Integration and… more
- Huntington Ingalls Industries (Roanoke, VA)
- …forward to meeting you. Job Description Do you enjoy challenging digital FPGA/ ASIC design problems? HII Mission Technologies is seeking out-of-the-box thinkers ... FPGA/ ASIC implementation tools (eg, ISE, Quartus, Synplify, Vivado, Design Compiler, Innovus, etc.) * Writing scripts for batched verification tasks:… more
- Belay Technologies (Laurel, MD)
- …runner up in 2020 and a finalist in 2021! Belay Technologies is seeking a Senior Hardware Design Engineer (HDE). The HDE will designs and tests new integrated ... Engineer (HDE) shall perform the following duties: + Senior to Mid-level FPGA Design Engineer to...+ Integrate new P&R tools, P&R tool updates, and ASIC or FPGA design libraries into Government's… more
- Qualcomm (Santa Clara, CA)
- …Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Master's degree in Science, Engineering, or related field and 3+ years of ASIC design , verification, validation, integration, or related work experience. OR PhD… more
- GrammaTech, Inc. (MD)
- …with RoT techniques including TPM + Experience with firmware-level code + FPGA physical design + Experience with device characterization or PUF techniques + ... with the other engineering personnel to coordinate the interrelated design and assure project completion + Applies ASIC...physical designers to successfully complete their specific P&R design tasks + Work with tool and library vendors… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the ... network and last-level caches , working closely with the physical design team on implementation, synthesis and...expertise is required as is a deep understanding of ASIC design flow including RTL design… more