- NVIDIA (Santa Clara, CA)
- …optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and ... you'll be doing: + You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting ... of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... of timing and physical design fundamentals + Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of… more
- BAE Systems (San Jose, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Senior Principal ASIC Design Engineer (Hybrid)** **95186BR** EEO Career ... career with BAE Systems. We are seeking a very senior level engineer to: + Design and...and verification methodologies (VCS simulator, UVM) + Proficient in ASIC /FPGA timing closure/area optimization techniques + Hands… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are ... What you'll be doing: + Drive physical design and timing of high-frequency and low-power designs + Focus on...NVIDIA's designs + Apply knowledge and gain experience in ASIC design including RTL and logic design, physical and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- NVIDIA (Santa Clara, CA)
- … Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working engineers to craft and ... + BS, MS, or PhD in Electrical Engineering, Computer Engineer , or related degree required (or equivalent experience) +...SOCs). + Relevant experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Display ASIC Design Engineer ! NVIDIA is seeking a passionate ASIC Design Engineers to craft and implement display subsystem in the ... coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. + Support the… more
- NVIDIA (Santa Clara, CA)
- … Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working engineers to craft and ... core and IP integration level RTL design, synthesis, functional verification, and timing analysis using groundbreaking CAD tools and using the latest process… more
- Amazon (Sunnyvale, CA)
- Description As a Sr. ASIC Design Engineer , you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop ... and design hardware accelerator IP in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional SOC development activities - Work with the… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers ... BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD)...+ You have experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing… more
- SpaceX (Sunnyvale, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your ... Sr. FPGA/ ASIC Design Engineer (Silicon Engineering) at... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your ... Sr. ASIC Design Engineer , DDR IP (Silicon...development and integration + Responsible for RTL design, synthesis, timing constraints, power estimation, and timing analysis… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency...members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... in Electrical or Computer Engineering with 5+ years experience in ASIC Design and Timing . + Proven understanding of circuit design and spice simulations.… more
- Qualcomm (San Jose, CA)
- …Engineering Group, Engineering Group > ASICS Engineering **General Summary:** The Digital ASIC Design Team is currently seeking candidates who will be responsible ... degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree… more
- Qualcomm (Santa Clara, CA)
- …transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, ... such as OFDM and OFDMA modulators and demodulators, transmit beamforming, timing and synchronization, RF impairment correction, adaptive filters . Working with… more
- SpaceX (Sunnyvale, CA)
- …front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...understanding of their impact on synthesis, physical design and timing closure + Deep understanding of ASIC … more
- Amazon (Sunnyvale, CA)
- …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We ... patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through...for high coverage on silicon - Review sign-off level timing closure using static timing analysis of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Logic Design Engineer ! Asa member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and ... tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you… more