- Cadence Design Systems, Inc. (San Jose, CA)
- …innovators who want to make an impact on the world of technology. Title Senior Applications Engineer - DDR Design IP Job Location: San Jose, CA Job ... Engineer , you will support the technical presales of DDR IP by generating collateral through simulations, synthesis and...simulations, synthesis and publications. As you grow into more senior roles, you will use your knowledge of different… more
- SpaceX (Sunnyvale, CA)
- Sr. ASIC Design Engineer , DDR IP (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... of enabling human life on Mars. SR. ASIC DESIGN ENGINEER , DDR IP (SILICON ENGINEERING) At SpaceX...critical milestones COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking hardworking and creative Senior Memory Controller Verification Engineer for our Tegra SoCs! At Nvidia, we have crafted a team of outstanding ... and AI! What you'll be doing: + As a senior member of our verification team, you'll understand the...issues related to the next generation of LPDDR and DDR memories + Ensure code and functional coverage of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Firmware Engineer for our Memory Subsystem Team! Widely considered to be one of the technology world's most desirable employers, ... silicon power-on to production. What you'll be doing: + Firmware development for DDR memory and memory subsystem, validation and debug of firmware and silicon… more
- RTX Corporation (Goleta, CA)
- …meaningful problems that create a safer, more secure world. Job Summary: The Senior Principal Firmware Design Engineer is responsible for requirements analysis ... a team environment. Responsibilities to Anticipate: As a critical team member, the Senior Principal FW Design Engineer will design, develop, integrate test the… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working ... What We Need To See: + BS, MS, or PhD in Electrical Engineering, Computer Engineer , or related degree required (or equivalent experience) + 5+ years of relevant and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer , you'll join a group of hard-working ... + BS, MS, or PhD in Electrical Engineering, Computer Engineer , or related degree required (or equivalent experience). +...of Memory Controller or PHY IPs. + Knowledge of DDR /LPDDR DRAM protocols + Prior experience in working… more
- NVIDIA (Santa Clara, CA)
- …processors across process, voltage, and temperatures + Work closely with Application Engineering teams to resolve customer issues in a time-critical environment. ... skills. Ways to stand out from the crowd: + Design background of DDR interface and datapath design with post-silicon validation and correlation to pre-silicon. +… more
- NVIDIA (Santa Clara, CA)
- …data analysis such as Python. + Experience with PC architecture, AGP/PCIe busses and DRAM/ DDR is a plus. NVIDIA is widely considered to be one of the technology ... be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) . NVIDIA accepts applications on an ongoing basis. NVIDIA is committed to fostering a… more
- Qualcomm (San Diego, CA)
- …Here are the key aspects of this position:_ _Memory System Expertise:_ + _As a senior memory system engineer , you'll need a deep understanding of SoC memory ... Systems Engineering **General Summary:** The _role of a Memory System Engineer at Qualcomm involves critical responsibilities related to memory subsystem… more
- SpaceX (Irvine, CA)
- …WA or Irvine, CA COMPENSATION & BENEFITS: Pay range: Physical Design STA/Timing Engineer / Senior : $160,000.00 - $220,000.00/per year Your actual level and base ... Sr. SOC Physical Design STA/Timing Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX...in IP integration (eg memories, I/Os, Analog IPs, SerDes, DDR etc.) + Experience in industry standard STA and… more
- SpaceX (Irvine, CA)
- …time to waveforms) COMPENSATION & BENEFITS: Pay range: SOC Emulation Verification Engineer / Senior : $160,000.00 - $220,000.00/per year Your actual level and ... Sr. SOC Emulation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX...UVM, and C/C++ verification environments + Working knowledge of DDR , PCIe, SPI, Ethernet, UART, eMMC, I2C + Knowledge… more
- Micron Technology, Inc. (Folsom, CA)
- …RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and ... **What's Encouraged Daily** + Focused, self-motivated semiconductor foundry interface engineer providing strategic and technical leadership across the semiconductor… more
- Micron Technology, Inc. (Folsom, CA)
- …RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and ... **What's Encouraged Daily** + Focused, self-motivated semiconductor foundry interface engineer providing strategic and technical leadership across the semiconductor… more
- Qualcomm (Santa Clara, CA)
- …end to end profiling with ability to identify bottlenecks in CPU, Cache, Buses, DDR , PCIE + Experience with Lauterbach JTAG Emulation and Trace software. + Working ... develop, create, modify, and validate embedded and cloud edge software, applications , and/or specialized utility programs. * Analyzes user needs, software… more
- Micron Technology, Inc. (Folsom, CA)
- …architecture for the next generation of high-performance memory that has wide-ranging applications and inspires change in memory systems? In the HBM Design ... blended into the same product, and most of the DDR or LPDDR design is based on the gate-level...innovative technical solutions + Provide advice and counsel to senior management on significant technical issues + Coordinate and… more