- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part ... to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPUs, GPUs, SoCs at… more
- NVIDIA (Santa Clara, CA)
- …MTBF analysis, logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing ... We are now looking for a motivated Senior ASIC Engineer, Timing to join... and Timing + Great understanding of timing and physical design fundamentals… more
- NVIDIA (Santa Clara, CA)
- …Electrical or Computer Engineering or equivalent experience. + 8+ years experience in Physical design / Timing . + Experience in full-chip/sub-chip Static ... next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our...of multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg… more
- NVIDIA (Santa Clara, CA)
- …years experience in ASIC Design and Timing + Great understanding of timing and physical design fundamentals + Hands-on experience in ASIC timing ... a good understanding of RTL/logic design skills as well as physical design /circuit skills for timing closure. + Excellent problem solving and debugging… more
- NVIDIA (Santa Clara, CA)
- …or Computer Engineering (or equivalent experience) + 5+ years of experience in Physical design / Timing + Experience in full-chip/sub-chip Static Timing ... generation and management, and timing convergence + Expertise in physical design , optimization, and ECO implementation eg cell sizing, buffering, VT swap +… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- Laser and Timing Systems Engineering Department Head Job ID 5857 Location SLAC - Menlo Park, CA Full-Time Regular **SLAC Job Postings** **Position Overview** The ... Accelerator Laboratory seeks a mechanical engineer to lead the Lasers and Timing Systems Engineering Department. LCLS is an X-ray Free Electron (FEL) facility… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are ... to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power designs + Focus on… more
- Microsoft Corporation (Mountain View, CA)
- …high-performance Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Physical Design Engineer** to work on leading edge ... to implement designs in Register Transfer Level (RTL) to Physical Design (PD) and RTL to Graphic...timing , Electro Migration and Voltage Drop (EMVD), and physical verification. Excellent communication skills will be needed to… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...+ Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop… more
- NVIDIA (Santa Clara, CA)
- …interconnect network and last-level caches , working closely with the physical design team on implementation, synthesis and timing closure as well as working ... a liaison between Logic design and Physical design teams responsible for achieving timing , area, performance and power goals of the unit. + Help define… more
- NVIDIA (Santa Clara, CA)
- …and Verification. + Strong background with hierarchical design approach, top-down design , budgeting, timing and physical convergence. + Familiar with ... strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics...floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …years of experience. Master's degree preferred. + Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is ... more of the following areas: Synthesis, Place and Route, timing and power signoff. + Understanding and proliferating Cadence...+ Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4… more
- NVIDIA (Santa Clara, CA)
- …meet performance, timing and power targets. + Deliver a synthesis/ timing clean design while working with the physical design team ensuring a routable ... We are looking for a Senior CPU Design Engineer! NVIDIA is...with architects, design engineers, verification engineers, and physical design engineers teams to accomplish your… more
- Amazon (Sunnyvale, CA)
- …guideline and model analysis. - Experience in timing analysis and working with physical design teams to close timing . - Experience in working with ... methodologies and EDA tools - Experience working with Synthesis, timing and design constraints Preferred Qualifications -...registers, and error handling. - Experience working closely with physical design teams to develop highly optimized… more
- NVIDIA (Santa Clara, CA)
- …and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and ... We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA...What you will be doing: + Working with architects, design leads, physical design leads… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...analysis on the design . + Drive the design and physical implementation of digital and/or… more
- Qualcomm (Santa Clara, CA)
- …Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the development and ... implementation of products at Qualcomm. This role requires strong knowledge of physical design tools (like Cadence or Synopsys), semiconductor processes, and an… more
- The Boeing Company (Mountain View, CA)
- … practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + ... has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** at Lead, Senior ...team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly… more
- SpaceX (Sunnyvale, CA)
- …work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at...(eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop,… more