- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Verification Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Amazon (Redmond, WA)
- …Kuiper team is looking for a Sr. Technical Program Manager with experience in ASIC / SOC and FPGA development, project management, and program management. The role ... this role you will: - Collaborate with engineering leaders ( SOC / ASIC leads) to create project...phases of Silicon development from architecture definition, RTL design, Verification , IP design, Physical design, post silicon… more
- SpaceX (Sunnyvale, CA)
- SOC / ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SOC / ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON...timing closure + Work closely with chip architecture, design verification , physical design, DFT, and power teams… more
- SpaceX (Irvine, CA)
- …SKILLS AND EXPERIENCE: + Understanding of ASIC design flow, methodologies, physical design, and verification + RTL experience to understand, trace and ... Sr. ASIC / SOC DFT Engineer (Silicon Engineering) at...evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools +… more
- SpaceX (Irvine, CA)
- ASIC Emulation Verification Engineer (Silicon Engineering)...based emulation in finding pre-silicon bugs at subsystem and SoC levels + Port ASIC and IP ... the ultimate goal of enabling human life on Mars. ASIC EMULATION VERIFICATION ENGINEER (SILICON ENGINEERING) At...time, time to waveforms) COMPENSATION & BENEFITS: Pay range: SOC Emulation Verification Engineer/Level I: $120,000.00 -… more
- Qualcomm (San Diego, CA)
- …This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification ... efficiency. **Qualifications:** + Minimum 3 years of DV experience using uvm/assertion based verification technologies + Experience in verifying complex SOC or … more
- Qualcomm (San Diego, CA)
- …working knowledge in the entire low power, high performance ASIC / SoC design flows (micro-architecture, RTL design, verification , synthesis, timing/STA, UPF, ... XR space. An ideal candidate will oversee definition, design, verification , and documentation for ASIC development for...CLP, LEC formal verification , DFT, physical design.) + Must have Hands-on experience in writing… more
- SpaceX (Irvine, CA)
- …phases of ASIC and/or FPGA design flow (eg synthesis, timing closure, verification ) + Work with ASIC backend/implementation teams as needed + Bring-up and ... FPGA/ ASIC Design Engineer (Silicon Engineering) at SpaceX Irvine,...digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks +… more
- Qualcomm (Santa Clara, CA)
- … Design Verification Engineer with strong CPU, ASIC design and verification fundamentals to work in Qualcomm's Global SOC team. This position offers the ... **The JOB** + As a member of the Global SOC Lower Power verification team, you will...Science, Engineering, or related field and 6+ years of ASIC design, verification , validation, integration, or related… more
- Amazon (Sunnyvale, CA)
- …in machine learning, computer vision and robotics. You will work closely with scientists, SoC Architects, software and verification to develop IP that meets the ... IP in Verilog HDL - Help define and own ASIC design methodologies - Lead cross functional SOC...registers, and error handling. - Experience working closely with physical design teams to develop highly optimized ASICs with… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …cryogenic operation and radiation hardening. + Floor planning, layout design and physical verification of active circuits. + Top-level simulations to validate ... ASIC Design Engineer Job ID 5683 Location SLAC...CAD toolsfor schematic entry, simulation, and layout design, including physical verification and top-level integration. + Solid… more
- NVIDIA (Santa Clara, CA)
- …GPU clock structure to satisfy all the architectural constraints. + Deliver clock information to SOC verification team, timing and DFT teams. + You will use Perl ... floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the...be doing: + Will be collaborating with other architects, ASIC designers and verification engineers to design… more
- SpaceX (Sunnyvale, CA)
- Sr. ASIC Design Engineer, DDR IP (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER, DDR IP (SILICON ENGINEERING) At SpaceX...quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects… more
- Meta (Austin, TX)
- …( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run Logic/ Physical Synthesis using ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. 2. Perform Power Estimation… more
- Micron Technology, Inc. (Minneapolis, MN)
- …and groundbreaking technology while rapidly growing your abilities. As our Staff ASIC Digital Synthesis Engineer role, you will contribute to the development of ... multidimensional designs involving the physical synthesis of complex integrated circuits. You will also...design optimization, ECOs, etc. + Test design using formal verification tools and functional verification environment. +… more
- Qualcomm (San Diego, CA)
- …candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. Also the candidate will have ... ASIC frontend development + Logic design, RTL coding, verification , synthesis, and timing closure + Hardware description languages...verification in validating low power design featurs at SoC and IP level. + Collaborate with company CAD… more
- Amazon (Sunnyvale, CA)
- …you will interface with cross-functional engineering and program/product management teams to develop ASIC / SOC solutions that will go into Amazon Devices. In this ... role you will: - Collaborate with engineering leaders ( SOC / ASIC leads) to create project...of Silicon development which are architecture definition, RTL design, Verification , IP design, Physical design, post silicon… more
- Qualcomm (Santa Clara, CA)
- …**Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the ... understanding of timing closure, clock tree synthesis, power optimization, and physical verification methodologies. Additionally, communication skills and the… more
- SpaceX (Irvine, CA)
- …make this possible, with the ultimate goal of enabling human life on Mars. SOC / ASIC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING) At SpaceX we're ... SOC Physical Design STA/Timing Engineer (Silicon... design flow + Work with systems and architecture, SOC integration, verification , DFT, mixed signal, IP… more
- Google (Sunnyvale, CA)
- …design. + Experience with silicon, emulation, FPGA validation and debug, functional verification , physical design, and DFT methodologies. + Experience with ... You will own deliverables to the cross-functional teams (eg, Physical Design, Verification , Validation, etc.) at various...the planning, creation, and delivery of top-level RTL/deliverables for ASIC and SOC projects from concept to… more