- Qualcomm (San Diego, CA)
- …seeking candidate whose primary role is to implement and validate low power design intent requirements at the SoC -level. The role also expands to power ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital...Work with design verification in validating low power design featurs at SoC … more
- General Motors (Warren, MI)
- …+ Master's degree in Electrical Engineering / Electronics + Previous experience with SoC design /application on a module or component level + Knowledge of ... **Job Description** We are seeking a **_Senior Design Release Engineer (DRE)_** to lead...production readiness activities for our cutting-edge next generation _System-on-a-Chip ( SoC ) semiconductors_ . Your efforts will be on the… more
- Google (Sunnyvale, CA)
- …machinery that goes into our cutting-edge data centers affecting millions of Google users. As a SoC Design Engineer , you will join a team working on SoC ... system hardware, and other cross-functional teams + Experience defining SoC IP interfaces and methodologies. Experience designing SOC...power all of Google's services. As a Hardware Engineer , you design and build the systems… more
- SpaceX (Irvine, CA)
- SOC Physical Design STA/Timing Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... make this possible, with the ultimate goal of enabling human life on Mars. SOC /ASIC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Google (Sunnyvale, CA)
- …software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the ... ASIC design methodologies for clock domain checks, reset checks and low power design . + Experience with silicon, emulation, FPGA validation and debug,… more
- Qualcomm (Santa Clara, CA)
- …Inc. **Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** A SOC Physical Design Engineer plays a crucial role in the ... Optimization: Implementing power -saving techniques and strategies to meet low- power design goals. * Physical Verification: Conducting design rule checks… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, to firmware, and algorithms.We are seeking an SoC Modeling ASIC Engineer to support C++/Python modeling and software ... and mapping software pipelines to the dedicated hardware accelerators. **Required Skills:** SoC Modeling ASIC Engineer Responsibilities: 1. Analyze the software… more
- SpaceX (Irvine, CA)
- …challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer /Senior: $160,000.00 - $220,000.00/per year Your actual level and ... Sr. SoC Implementation Engineer (Silicon Engineering) at...process and technology nodes for high speed and low power consumption + Software design and development… more
- SpaceX (Sunnyvale, CA)
- … intent verification and post synthesis timing validation flows + Execute low power design and physical synthesis, deploying knowledge of unified power ... SOC /ASIC Synthesis & Front-End STA Engineer ...closely with chip architecture, design verification, physical design , DFT, and power teams to achieve… more
- Google (Sunnyvale, CA)
- …software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the ... affecting millions of Google users. As an ASIC and SoC System Level Test Engineer , you will...product engineering activities. You will work with ASIC Architecture, Design , and Pre-silicon SoC Verification teams to… more
- SpaceX (Irvine, CA)
- SoC /ASIC Physical Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SOC /ASIC PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At...with physical design (PD) team to close design issues + Execute SOC GDSII integration,… more
- SpaceX (Irvine, CA)
- …necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: FPGA/ASIC Design Engineer /Level I: $120,000.00 - $145,000.00/per year FPGA/ASIC ... SoC Implementation Engineer (Silicon Engineering) at SpaceX...Design Engineer /Level II: $140,000.00 - $170,000.00/per year Your actual level and… more
- SpaceX (Irvine, CA)
- Sr. ASIC/ SOC DFT Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. SR. ASIC/ SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...process and technology nodes for high speed and low power consumption + Experience with high reliability design… more
- Qualcomm (Santa Clara, CA)
- …Power verification team, you will be responsible for verifying the ASIC low power design , architecture and micro-architecture of by applying advanced low ... Engineering **General Summary:** We are looking for an ASIC Design Verification Engineer with strong CPU, ASIC... and verification fundamentals to work in Qualcomm's Global SOC team. This position offers the rare opportunity to… more
- Palo Alto Networks (Santa Clara, CA)
- …and thrive, together! **Your Career** Come join Palo Alto Networks as a Staff SOC Automation Engineer on the Information Security team. As a member of ... beyond! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is...to perform in a key role in our internal SOC ; Design , test and build inspiring automation… more
- Google (Sunnyvale, CA)
- …software and networking technologies that power all of Google's services. As a Hardware Engineer , you design and build the systems that are the heart of the ... + Architect and Design ASIC models for Emulation/FPGA Prototypes. Design SoC configurations and IP models to optimize for simulation performance/run times. +… more
- Qualcomm (San Diego, CA)
- …3 years of experience is required and proficiency in handling tools such as Design compiler, Fusion compiler, Primetime, Conformal low power , LEC. Scripting ... + Work closely with RTL design , physical design teams to optimize area, performance and power...design constraints to achieve timing closure of complex soc cores. + Tabulate metrics results for QOR comparison.… more
- Google (Sunnyvale, CA)
- …of experience in test engineering or product engineering. + Experience in ASIC or SoC DFT test development, bring-up, or debug for NPI prototypes or High Volume ... this role, you will help build the SoCs that power these data centers by driving development of comprehensive...into the field to close the loop back to design and test for the next generations of chips.… more
- ManpowerGroup (San Jose, CA)
- …Jira + Familiar with revision control systems like Git **Nice to have:** + Low power design background for front-end + Background in high speed IOs and Protocol ... **We Are:** The Silicon Design group is a diverse team of world...an unparalleled time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal… more
- ManpowerGroup (Phoenix, AZ)
- …Power integrity analysis at block and top level, including EM, IR & ESD analysis, power reduction techniques in SOC design . + Power constraints ... **Role: Physical Design - Power Integrity Flow Development Engineer... analysis in vector and vector-less modes of ASIC SoC design at different design … more