- SpaceX (Sunnyvale, CA)
- SOC/ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... with the ultimate goal of enabling human life on Mars. SOC/ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm Hardware Engineer , you will plan, design, optimize, verify, and test electronic systems. Qualcomm ... for the development of SoC designs. Roles/Responsibilities: Job responsibilities include RTL Synthesis using state of the art Physical Synthesis Tools; Timing… more
- ManpowerGroup (Phoenix, AZ)
- **L3** (7-15 yrs.) or **L4** (15+ yrs.)) USC or GC ONLY ONSITE **SOC Integration/ STA / Synthesis Engineer ** Required Skills: + Develop and own physical design ... & timing ECO in advanced technology nodes + Develop & document STA & Synthesis strategies. Interact with methodology teams to address challenges related to new… more
- SpaceX (Irvine, CA)
- SOC Physical Design STA /Timing Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN STA /TIMING ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
- Microsoft Corporation (Mountain View, CA)
- …in the industry. The Physical Design team is looking for Principal Static Timing Analysis ( STA ) Engineer to join us as we continue to build a world-class team ... from you! **Responsibilities** As a Principal Static Timing Analysis ( STA ) Engineer , you will be responsible for...thereafter. **Preferred Qualifications:** + Strong expertise in extraction and STA plus or more of the following: synthesis… more
- Amazon (San Diego, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. -… more
- Qualcomm (Austin, TX)
- …( STA ) of DSP. Work on activities related to placement, clock tree synthesis (CTS), routing, STA , ECO generation and overall physical design convergence. ... static timing analysis and ECO generation. Update the physical design implementation and STA flows for optimum PPA (power, performance, and area). + Perform physical… more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power Analysis and… more
- Cadence Design Systems, Inc. (Columbia, MD)
- …planning, power grid design, place and route, clock tree synthesis , timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR ... signoff, DFM Closure. Job Description - Physical Design, including: floorplan, placement, CTS, routing, etc. - Physical Verification - Static Timing Analysis - EM/IR Analysis Job Qualification: - Extensive knowledge of the design rule for the process of N7/N5… more
- Micron Technology, Inc. (Minneapolis, MN)
- …groundbreaking technology while rapidly growing your abilities. As our Staff ASIC Digital Synthesis Engineer role, you will contribute to the development of ... **In our hybrid role** , you will develop and operate front-end Synthesis flows, including STA , constraint management, Lint/CDC/RDC, front-end/back-end netlist… more
- Meta (Austin, TX)
- …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... corresponding reset sequence for RDC. 8. Develop Timing Constraints for RTL- Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze… more
- Microsoft Corporation (Santa Clara, CA)
- …or related field. + 7+ years of physical design experience, including hands-on experience in synthesis , place & route, and STA . + 4+ years of experience with ... We are looking for a **Physical Design Methodology Engineer ** . As part of our DPU silicon...Qualifications:** + 10+ years of physical design experience (including synthesis , place & route, LEC, STA , physical… more
- Amazon (San Diego, CA)
- …design and help review or create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC teams to ... this role you will: * As the physical implementation engineer you will set up the flow for both...* 7+ years of experience in ASIC implementation, ie, synthesis , STA and working with DFT, P&R… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... frontend and backend implementation from RTL to gds2, including synthesis , equivalence checking, floor-planning, timing constraints, timing and power convergence,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... generation of CPU, GPU or SOC designs. + Owning STA of large subsystems and full chip designs or...or at block-level with additional responsibilities for block level synthesis /optimization + You will be responsible for all aspects… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... with 6+ years experience in Physical Design + Expertise in physical synthesis and deep understanding of RTL/logic and equivalence checking to achieve better… more
- Cadence Design Systems, Inc. (Austin, TX)
- …impact on the world of technology. The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer ... their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus...and physical), Place and Route (primary focus ) , STA / SDC skills and some experience supporting tapeouts… more
- Qualcomm (San Diego, CA)
- …**Qualifications** + Must have Hands-on experience in RTL coding, RTL/gate level sim, synthesis , timing/ STA , UPF + Strong working knowledge in the entire low ... power, high performance ASIC/SoC design flows (micro-architecture, RTL design, verification, synthesis , timing/ STA , UPF, CLP, LEC formal verification, DFT,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …customers in the areas of Digital Design Implementation & Signoff including Synthesis , Place and Route, Design Closure, and timing/power signoff + Guide customers ... (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) + Experience with...tools in the IC digital implementation & signoff flows ( STA tools) + Strong STA and SDC… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …gate level simulations to verify functionality. + Perform and help debug Synthesis / STA scripts/constraints. + Participate in development of Application notes, ... IP. + Verilog RTL design and gate level verification experience. + Synthesis and STA experience, back-end experience is a plus + Familiarity with industry… more