- Qualcomm (San Diego, CA)
- …and power analysis feedback. Candidates should have strong knowledge of memory systems , caching, PPA tradeoffs, RTL design , ASIC flows, synthesis tools, ... architecture tradeoff analysis and performance trouble shooting. + Experience with cache /memory controller micro-architecture, RTL design and implementation is a… more
- Qualcomm (San Diego, CA)
- …and design of Platform infrastructure HW components such as Interconnect (NOC), System Cache , Memory controllers and System MMU that are implemented ... HW-&-SW feature trade-off, and the complete silicon HW end-2-end design flow. This is a challenging position, defining and...Memory Controller, Interrupt Handler) + Strong knowledge in Platform System Architecture (example : ARM or X86 or RISC-V… more
- Qualcomm (San Diego, CA)
- …and design of Platform infrastructure HW components such as Memory controllers, System cache , System MMU and Interconnect that are implemented in ... System performance architects. Key Deliverables: + Modeling and analysis of system cache , memory controller scheduling algorithms, and features + Develop… more
- Qualcomm (San Diego, CA)
- …, Austin and Boxborough and across all levels. **What you will be doing** : Micro- architect and design RTL for blocks and modules of Adreno GPU architecture ... graphics pipelines, memory subsystem and interconnect, and power and system level design Identify advanced ways to...Experience in designing RTL for GPU, CPU, DSP, Machine-Learning, cache , controller, video, display, camera blocks in ASIC is… more